Datasheet > MC100ES6039DWR2

MC100ES6039DWR2

更新时间： 2024-11-05 21:54:11

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		时钟发生器逻辑集成电路光电二极管驱动
页数	文件大小	规格书
8页	236K
描述
3.3V ECL/PECL/HSTL/LVDS 2/4, 4/6 Clock Generation Chip

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MC100ES6039DWR2 数据手册

MC100ES6039

Rev 2, 06/2005

Freescale Semiconductor

Technical Data

3.3 V ECL/PECL/HSTL/LVDS ÷2/4,

÷4/6 Clock Generation Chip

MC100ES6039

The MC100ES6039 is a low skew ÷2/4, ÷4/6 clock generation chip designed

explicitly for low skew clock generation applications. The internal dividers are

synchronous to each other, therefore, the common output edges are all precisely

aligned. The device can be driven by either a differential or single-ended ECL or,

if positive power supplies are used, LVPECL input signals. In addition, by using

the V_BBoutput, a sinusoidal source can be AC coupled into the device.

The common enable (EN) is synchronous so that the internal dividers will only

be enabled/disabled when the internal clock is already in the LOW state. This

avoids any chance of generating a runt clock pulse on the internal clock when the

device is enabled/disabled as can happen with an asynchronous control. The

internal enable flip-flop is clocked on the falling edge of the input clock, therefore,

all associated specification limits are referenced to the negative edge of the clock

input.

Upon startup, the internal flip-flops will attain a random state; therefore, for

systems which utilize multiple ES6039s, the master reset (MR) input must be

asserted to ensure synchronization. For systems which only use one ES6039,

the MR pin need not be exercised as the internal divider design ensures

synchronization between the ÷2/4 and the ÷4/6 outputs of a single device. All V_CC

and V_EEpins must be externally connected to power supply to guarantee proper

operation.

DW SUFFIX

20-LEAD SOIC PACKAGE

CASE 751D-07

EG SUFFIX

20-LEAD TSSOP PACKAGE

Pb-FREE PACKAGE

CASE 751D-07

ORDERING INFORMATION

Device

Package

SO-20

The 100ES Series contains temperature compensation.

MC100ES6039DW

MC100ES6039DWR2

MC100ES6039EG

MC100ES6039EGR2

Features

SO-20

•

Maximum Frequency >1.0 GHz Typical

SO-20 (Pb-Free)

50 ps Output-to-Output Skew

PECL Mode Operating Range: V_CC= 3.135 V to 3.8 V with V_EE= 0 V

ECL Mode Operating Range: V_CC= 0 V with V_EE= –3.135 V to –3.8 V

Open Input Default State

Synchronous Enable/Disable

Master Reset for Synchronization of Multiple Chips

V_BBOutput

LVDS and HSTL Input Compatible

20-Lead Pb-Free Package Available

12 3 4 5 6 7 8

中文翻译

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与MC100ES6039DWR2相关器件

型号	品牌	获取价格	描述	数据表
MC100ES6039EG	FREESCALE	获取价格	3.3V ECL/PECL/HSTL/LVDS 2/4, 4/6 Clock Generation Chip
MC100ES6039EGR2	FREESCALE	获取价格	3.3V ECL/PECL/HSTL/LVDS 2/4, 4/6 Clock Generation Chip
MC100ES6056	IDT	获取价格	2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
MC100ES6056	FREESCALE	获取价格	2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer
MC100ES6056DT	FREESCALE	获取价格	2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer
MC100ES6056DT	IDT	获取价格	2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
MC100ES6056DT	MOTOROLA	获取价格	100E SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20, TSSOP-20
MC100ES6056DTR2	IDT	获取价格	2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
MC100ES6056DTR2	FREESCALE	获取价格	2.5 V/3.3 V ECL/PECL/LVDS Dual Differential 2:1 Multiplexer
MC100ES6056DTR2	MOTOROLA	获取价格	100E SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20, TSSOP-20

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