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MC100ES6017EG

更新时间： 2024-11-05 21:54:47
品牌 Logo 应用领域
安森美 - ONSEMI 接口集成电路光电二极管
页数 文件大小 规格书
8页 122K
描述
3.3V ECL/PECL Quad Differential Receiver

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MC100ES6017EG 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10H/100H680 is a dual supply 4–bit differential ECL bus to TTL  
bus transceiver. It is designed to allow the system designer to no longer be  
limited in bus speed associated with standard TTL busses. Using a  
differential ECL Bus will increase the frequency of operation and increase  
noise immunity.  
Both the TTL and the ECL ports are capable of driving a bus. The ECL  
outputs have the ability to drive 25 Ω, allowing both ends of the bus line to be  
terminated in the characteristic impedance of 50 Ω. The TTL outputs are  
specified to source 15 mA and sink 48 mA, allowing the ability to drive highly  
capacitive loads.  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776–02  
The ECL output levels are V  
approximately equal to –1.0 V and V  
OH  
OL  
cutoff equal to –2.0 V (VTT). When the ECL ports are disabled both EIOx and  
EIOxB go to the V cutoff level. The ECL input receivers have special  
OL  
circuitry which detects this disabled condition, prevents oscillation, and  
forces the TTL output to the low state. The noise margin in this disabled state  
is greater than 600 mV. Multiple ECL V  
switching noise.  
pins are utilized to minimize  
CCO  
The TTL ports have standard levels. The TTL input receivers have PNP  
input devices to significantly reduce loading. Multiple TTL power and ground  
pins are utilized to minimize switching noise.  
The control pins (EDIR and ECEB) of the 10H version is compatible with  
MECL 10H ECL logic levels. The control pins of the 100H version are  
compatible with 100K levels.  
•
•
•
Differential ECL Bus (25 Ω) I/O Ports  
High Drive TTL Bus I/O Ports  
Extra TTL and ECL Power/Ground Pins to Minimize  
Switching Noise  
Dual Supply  
Direction and Chip Enable Control Pins  
PIN DESCRIPTIONS  
Pin  
Symbol  
Function  
1
GT1  
TTL Ground 1  
TTL I/O Bit 0  
2
TIO0  
•
•
3
4
5
TDIR  
EDIR  
EIO0  
TTL Direction Control  
ECL Direction Control  
ECL I/O Bit 0  
6
7
8
9
VCCO1  
EIO0B  
VEE  
ECL VCC 1 (0V) – Outputs  
ECL I/O Bit 0 Bar  
ECL Supply (–5.2/–4.5V)  
ECL I/O Bit 1  
Pinout: 28–Lead PLCC (Top View)  
EIO1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
VCCO2  
EIO1B  
EIO2  
VCCO3  
EIO2B  
VCCE  
EIO3  
VCCO4  
EIO3B  
ECEB  
TCEB  
TIO3  
GT4  
VT2  
GT3  
TIO2  
TIO1  
GT2  
VT1  
ECL VCC 2 (0V) – Outputs  
ECL I/O Bit 1 Bar  
ECL I/O Bit 2  
ECL VCC 3 (0V) – Outputs  
ECL I/O Bit 2 Bar  
ECL VCC (0V)  
25  
24  
23  
22  
21  
20  
19  
T101  
GT2  
VT1  
26  
27  
28  
18  
17  
16  
EIO3B  
V
CCO4  
EIO3  
ECL I/O Bit 3  
ECL VCC 4 (0V) – Outputs  
ECL I/O Bit 3 Bar  
ECL Chip Enable Bar Control  
TTL Chip Enable Bar Control  
TTL I/O Bit 3  
TTL Ground 4  
TTL Supply 2 (5V)  
TTL Ground 3  
TTL I/O Bit 2  
TTL I/O Bit 1  
TTL Ground 2  
TTL Supply 1 (5V)  
GT1  
TIO0  
TDIR  
EDIR  
1
2
3
4
15  
14  
13  
12  
V
CCE  
EIO2B  
V
CCO3  
EIO2  
5
6
7
8
9
10  
11  
9/96  
REV 6  
Motorola, Inc. 1996  
12345678

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