Datasheet > MC100ES6014

MC100ES6014

更新时间： 2024-09-16 11:10:55

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		时钟驱动器
页数	文件大小	规格书
8页	258K
描述
2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver

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MC100ES6014 数据手册

MC100ES6014

Rev 3, 06/2005

Freescale Semiconductor

Technical Data

2.5 V/3.3 V 1:5 Differential

ECL/PECL/HSTL/LVDS Clock Driver

MC100ES6014

The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock

distribution in mind, accepting two clock sources into an input multiplexer. The

ECL/PECL input signals can be either differential or single-ended (if the V_BB

output is used). HSTL and LVDS inputs can be used when the ES6014 is

operating under PECL conditions.

DT SUFFIX

20-LEAD TSSOP PACKAGE

CASE 948E-03

The ES6014 specifically guarantees low output-to-output skew. Optimal

design, layout, and processing minimize skew within a device and from device to

device.

To ensure that the tight skew specification is realized, both sides of any

differential output need to be terminated identically into 50 Ω even if only one

output is being used. If an output pair is unused, both outputs may be left open

(unterminated) without affecting skew.

The common enable (EN) is synchronous, outputs are enabled/disabled in the

LOW state. This avoids a runt clock pulse when the device is enabled/disabled

as can happen with an asynchronous control. The internal flip flop is clocked on

the falling edge of the input clock; therefore, all associated specification limits are

referenced to the negative edge of the clock input.

EJ SUFFIX

20-LEAD TSSOP PACKAGE

Pb-FREE PACKAGE

CASE 948E-03

The MC100ES6014, as with most other ECL devices, can be operated from a

positive V_CCsupply in PECL mode. This allows the ES6014 to be used for high

performance clock distribution in +3.3 V or +2.5 V systems. Single ended CLK

input pin operation is limited to a V_CC≥ 3.0 V in PECL mode, or V_EE≤ –3.0 V in

ECL mode. Designers can take advantage of the ES6014's performance to

distribute low skew clocks across the backplane or the board.

ORDERING INFORMATION

Device

Package

TSSOP-20

MC100ES6014DT

MC100ES6014DTR2

MC100ES6014EJ

MC100ES6014EJR2

TSSOP-20

TSSOP-20 (Pb-Free)

Features

•

25 ps Within Device Skew

400 ps Typical Propagation Delay

Maximum Frequency > 2 GHz Typical

The 100 Series Contains Temperature Compensation

PECL and HSTL Mode: V_CC= 2.375 V to 3.8 V with V_EE= 0 V

ECL Mode: V_CC= 0 V with V_EE= –2.375 V to –3.8 V

LVDS and HSTL Input Compatible

Open Input Default State

20-Lead Pb-Free Package Available

12 3 4 5 6 7 8

中文翻译

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与MC100ES6014相关器件

型号	品牌	获取价格	描述	数据表
MC100ES6014DT	FREESCALE	获取价格	2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
MC100ES6014DTR2	FREESCALE	获取价格	2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
MC100ES6014DW	MOTOROLA	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, PLASTI
MC100ES6014DW	NXP	获取价格	100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, PLASTI
MC100ES6014DWR2	MOTOROLA	获取价格	Low Skew Clock Driver, 100E Series, 5 True Output(s), 0 Inverted Output(s), ECL, PDSO20, P
MC100ES6014EJ	FREESCALE	获取价格	2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
MC100ES6014EJR2	FREESCALE	获取价格	2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
MC100ES6017	FREESCALE	获取价格	3.3V ECL/PECL Quad Differential Receiver
MC100ES6017	ONSEMI	获取价格	3.3V ECL/PECL Quad Differential Receiver
MC100ES6017DW	ONSEMI	获取价格	3.3V ECL/PECL Quad Differential Receiver

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