5秒后页面跳转
捷配首页

Datasheet > MC100ES6014DWR2
MC100ES6014DWR2 PDF预览

MC100ES6014DWR2

更新时间： 2024-11-06 17:45:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 117K
描述
Low Skew Clock Driver, 100E Series, 5 True Output(s), 0 Inverted Output(s), ECL, PDSO20, PLASTIC, SOIC-20

阅读下载

中文翻译

获取价格

MC100ES6014DWR2 技术参数

生命周期：Transferred包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.69其他特性：ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V
系列：100E输入调节：DIFFERENTIAL MUX
JESD-30 代码：R-PDSO-G20长度：12.8 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER功能数量：1
反相输出次数：端子数量：20
实输出次数：5最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：0.475 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.025 ns
座面最大高度：2.65 mm最大供电电压 (Vsup)：3.8 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

MC100ES6014DWR2 数据手册

 浏览型号MC100ES6014DWR2的Datasheet PDF文件第2页浏览型号MC100ES6014DWR2的Datasheet PDF文件第3页浏览型号MC100ES6014DWR2的Datasheet PDF文件第4页浏览型号MC100ES6014DWR2的Datasheet PDF文件第5页浏览型号MC100ES6014DWR2的Datasheet PDF文件第6页 
ꢀꢁ ꢂ ꢁꢃ ꢁ ꢄꢅ  
SEMICONDUCTOR TECHNICAL DATA  
Order Number: MC100ES6014/D  
Rev 0, 05/2003  
ꢀ
ꢆ
ꢁ
ꢇ
ꢂ
ꢈ
ꢃ
ꢉ
ꢄ
ꢅ
ꢄ
ꢊ
ꢆ
ꢋ
ꢇ
ꢇ
ꢁ
ꢋ
ꢈ
ꢉ
ꢉ
ꢆ
ꢌ
ꢊ
ꢍ
ꢋ
ꢁ
ꢎ
ꢅ
ꢈ
ꢇ
ꢏ
ꢌ
ꢄ
ꢐ
ꢋ
ꢑ
ꢆ
ꢀ
ꢙ
ꢍ
ꢡ
ꢡ
ꢘ
ꢜ
ꢢ
ꢡ
ꢍ
ꢣ
ꢑ
ꢒ
ꢓ
ꢒ
ꢔ
ꢕ
ꢐ
ꢖ
ꢗ
ꢘ
ꢙ
ꢄ
ꢊ
ꢚ
ꢘ
ꢙ
ꢄ
ꢊ
ꢛ
ꢜ
ꢂ
ꢄ
ꢊ
ꢄ
ꢉ
ꢏ
ꢜ
ꢙ
ꢗ
ꢝꢞ  
ꢟ
ꢏ
ꢓ
ꢐ
ꢠ
ꢒ
ꢓ
The MC100ES6014 is a low skew 1–to–5 differential driver, designed  
with clock distribution in mind, accepting two clock sources into an input  
multiplexer. The ECL/PECL input signals can be either differential or  
single–ended (if the VBB output is used). HSTL and LVDS inputs can be  
used when the ES6014 is operating under PECL conditions.  
DT SUFFIX  
20 LEAD TSSOP PACKAGE  
CASE 948E  
The ES6014 specifically guarantees low output–to–output skew. Opti-  
mal design, layout, and processing minimize skew within a device and  
from device to device.  
To ensure that the tight skew specification is realized, both sides of any  
differential output need to be terminated identically into 50 W even if only  
one output is being used. If an output pair is unused, both outputs may be  
left open (unterminated) without affecting skew.  
DW SUFFIX  
20 LEAD SOIC PACKAGE  
CASE 751D  
The common enable (EN) is synchronous, outputs are enabled/ dis-  
abled in the LOW state. This avoids a runt clock pulse when the device is  
enabled/disabled as can happen with an asynchronous control. The inter-  
nal flip flop is clocked on the falling edge of the input clock; therefore, all  
associated specification limits are referenced to the negative edge of the  
clock input.  
ORDERING INFORMATION  
The MC100ES6014, as with most other ECL devices, can be operated  
from a positive VCC supply in PECL mode. This allows the ES6014 to be  
used for high performance clock distribution in +3.3 V or +2.5 V systems.  
Single ended CLK input pin operation is limited to a VCC ≥ 3.0 V in PECL  
mode, or VEE ≤ –3.0 V in ECL mode. Designers can take advantage of the  
ES6014’s performance to distribute low skew clocks across the back-  
plane or the board.  
Device  
Package  
MC100ES6014DT  
TSSOP–20  
TSSOP–20  
SO–20  
MC100ES6014DTR2  
MC100ES6014DW  
MC100ES6014DWR2  
SO–20  
7
Features  
• 100 ps Device–to–Device Skew  
• 25 ps Within Device Skew  
• 400 ps Typical Propagation Delay  
• Maximum Frequency > 2 GHz Typical  
• The 100 Series Contains Temperature Compensation  
• PECL and HSTL Mode: VCC = 2.375 V to 3.8 V  
with VEE = 0 V  
• ECL Mode: VCC = 0 V  
with VEE = –2.375 V to –3.8 V  
• LVDS and HSTL Input Compatible  
• Open Input Default State  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA  
665  
123456

中文翻译

下载PDF

与MC100ES6014DWR2相关器件

型号 品牌 获取价格 描述 数据表
MC100ES6014EJ FREESCALE

获取价格

 		2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
MC100ES6014EJR2 FREESCALE

获取价格

 		2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
MC100ES6017 FREESCALE

获取价格

 		3.3V ECL/PECL Quad Differential Receiver
MC100ES6017 ONSEMI

获取价格

 		3.3V ECL/PECL Quad Differential Receiver
MC100ES6017DW ONSEMI

获取价格

 		3.3V ECL/PECL Quad Differential Receiver
MC100ES6017DW FREESCALE

获取价格

 		3.3V ECL/PECL Quad Differential Receiver
MC100ES6017DWR2 FREESCALE

获取价格

 		3.3V ECL/PECL Quad Differential Receiver
MC100ES6017DWR2 ONSEMI

获取价格

 		3.3V ECL/PECL Quad Differential Receiver
MC100ES6017EG ONSEMI

获取价格

 		3.3V ECL/PECL Quad Differential Receiver
MC100ES6017EG FREESCALE

获取价格

 		3.3V ECL/PECL Quad Differential Receiver

与MC100ES6014DWR2相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证