MC100EP210SFA

更新时间： 2024-11-04 22:08:15

品牌	Logo	应用领域
安森美 - ONSEMI		时钟驱动器
页数	文件大小	规格书
8页	70K
描述
2.5V1:5 Dual Differential LVDS Compatible Clock Driver

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MC100EP210SFA 数据手册

MC100EP210S

2.5VĄ1:5 Dual Differential

LVDS Compatible Clock

Driver

The MC100EP210S is a low skew 1–to–5 dual differential driver,

designed with LVDS clock distribution in mind. The LVDS or

LVPECL input signals are differential and the signal is fanned out to

five identical differential LVDS outputs.

The EP210S specifically guarantees low output–to–output skew.

Optimal design, layout, and processing minimize skew within a device

and from device to device.

http://onsemi.com

MARKING

DIAGRAM*

Two internal 50 W resistors are provided across the inputs. For

LVDS inputs, VTA and VTB pins should be unconnected. For

MC100

EP210S

LVPECL inputs, VTA and VTB pins should be connected to the V

(V –2.0 V) supply.

LQFP–32

FA SUFFIX

CASE 873A

AWLYYWW

Designers can take advantage of the EP210S performance to

distribute low skew LVDS clocks across the backplane or the board.

Special considerations are required for differential inputs under No

Signal conditions to prevent instability.

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

• 20 ps Typical Output–to–Output Skew

• 85 ps Typical Device–to–Device Skew

• 550 ps Typical Propagation Delay

• The 100 Series Contains Temperature Compensation

• Maximum Frequency > 1 GHz Typical

*For additional information, refer to Application Note

AND8002/D

• Operating Range: V = 2.375 V to 2.625 V with V = 0 V

• Internal 50 W Input Termination Resistors

• LVDS Input/Output Compatible

ORDERING INFORMATION

Device

Package

Shipping

MC100EP210SFA

LQFP–32 250 Units/Tray

MC100EP210SFAR2 LQFP–32 2000 Tape & Reel

Semiconductor Components Industries, LLC, 2002

Publication Order Number:

May, 2002 – Rev. 5

MC100EP210S/D

12 3 4 5 6 7 8

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