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MC100EP223FA

更新时间： 2024-09-15 20:36:43
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动逻辑集成电路
页数 文件大小 规格书
5页 115K
描述
Low Skew Clock Driver, 100E Series, 22 True Output(s), 0 Inverted Output(s), ECL, PQFP64, PLASTIC, TQFP-64

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MC100EP223FA 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：LFQFP,Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.92
系列：100E输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-PQFP-G64JESD-609代码：e0
长度：10 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：64实输出次数：22
最高工作温度：85 °C最低工作温度：
输出特性：OPEN-EMITTER封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：ECL
温度等级：OTHER端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10 mm最小 fmax：250 MHz
Base Number Matches：1

MC100EP223FA 数据手册

 浏览型号MC100EP223FA的Datasheet PDF文件第2页浏览型号MC100EP223FA的Datasheet PDF文件第3页浏览型号MC100EP223FA的Datasheet PDF文件第4页浏览型号MC100EP223FA的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
The MC100EP223 is a low skew 1–to–22 differential driver, designed  
with clock distribution in mind. It accepts two clock sources into an input  
multiplexer. The selected signal is fanned out to 22 identical differential  
outputs.  
LOW–VOLTAGE  
1:22 DIFFERENTIAL  
PECL/HSTL CLOCK DRIVER  
•
•
•
•
•
•
•
200ps Part–to–Part Skew  
50ps Output–to–Output Skew  
Differential Design  
Open Emitter HSTL Compatible Outputs  
3.3V V  
CC  
Both PECL and HSTL Inputs  
75kΩ Input Pulldown Resistors  
The EP223 is specifically designed, modeled and produced with low  
skew as the key goal. Optimal design and layout serve to minimize  
gate–to–gate skew within a device, and empirical modeling is used to  
determine process control limits that ensure consistent t distributions  
pd  
from lot to lot. The net result is a dependable, guaranteed low skew  
device.  
FA SUFFIX  
64–LEAD TQFP PACKAGE  
CASE 840F–02  
The EP223 HSTL outputs are not realized in the conventional  
manner. To minimize part–to–part and output–to–output skew, the HSTL  
compatible output levels are generated with an open emitter  
architecture. The outputs are pulled down with 50Ω to ground, rather  
than the typical 50Ω to V  
pullup of a “standard” HSTL output.  
DDQ  
Because the HSTL outputs are pulled to ground, the EP223 does not  
utilize the V supply of the HSTL standard. The output levels are  
DDQ  
derived from V  
.
CC  
In the case of an asynchronous control, there is a chance of  
generating a ‘runt’ clock pulse when the device is enabled/disabled. To  
avoid this, the output enable (OE) is synchronous so that the outputs  
will only be enabled/disabled when they are already in the LOW state.  
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into  
50Ω, even if only one side is being used. In most applications, all 22 differential pairs will be used and therefore terminated. In  
the case where fewer than 22 pairs are used, it is necessary to terminate at least the output pairs on the same package side as  
the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of  
propagation delay (on the order of 10–20ps) of the output(s) being used which, while not being catastrophic to most designs, will  
mean a loss of skew margin.  
This document contains information on a product under development. Motorola reserves the right to change or  
discontinue this product without notice.  
08/99  
REV 1  
Motorola, Inc. 1999  
12345

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