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MC100EP29DT

更新时间： 2024-11-04 21:54:11
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
8页 77K
描述
3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset

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中文翻译

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MC100EP29DT 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-20针数：20
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：7.5
Is Samacsys：N其他特性：NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
系列：100EJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：6.5 mm
逻辑集成电路类型：D FLIP-FLOP位数：1
功能数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：RAIL峰值回流温度（摄氏度）：260
电源：-4.5 V传播延迟（tpd）：0.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

MC100EP29DT 数据手册

 浏览型号MC100EP29DT的Datasheet PDF文件第2页浏览型号MC100EP29DT的Datasheet PDF文件第3页浏览型号MC100EP29DT的Datasheet PDF文件第4页浏览型号MC100EP29DT的Datasheet PDF文件第5页浏览型号MC100EP29DT的Datasheet PDF文件第6页浏览型号MC100EP29DT的Datasheet PDF文件第7页 
MC10EP29, MC100EP29  
3.3V / 5VĄECL Dual  
Differential Data and Clock  
D Flip-Flop With Set and  
Reset  
http://onsemi.com  
The MC10/100EP29 is a dual master–slave flip–flop. The device  
features fully differential Data and Clock inputs as well as outputs.  
The MC10/100EP29 is functionally equivalent to the  
MC10/100EL29. Data enters the master latch when the clock is LOW  
and transfers to the slave upon a positive transition on the clock input.  
The differential inputs have special circuitry which ensures device  
stability under open input conditions. When both differential inputs  
MARKING  
DIAGRAM*  
20  
20  
are left open the D input will pull down to V and the D input will  
EE  
xxx  
EP29  
ALYW  
1
bias around V /2. The outputs will go to a defined state, however the  
CC  
TSSOP–20  
DT SUFFIX  
CASE 948E  
state will be random based on how the flip flop powers up.  
Both flip flops feature asynchronous, overriding Set and Reset  
inputs. Note that the Set and Reset inputs cannot both be HIGH  
simultaneously.  
1
xxx = MC10 or 100  
A
L
Y
W
The V pin, an internally generated voltage supply, is available to  
BB  
= Assembly Location  
this device only. For single-ended input conditions, the unused  
= Wafer Lot  
= Year  
= Work Week  
differential input is connected to V as a switching reference voltage.  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
The 100 Series contains temperature compensation.  
BB  
*For additional information, see Application Note  
AND8002/D  
• Maximum Frequency > 3 GHz Typical  
• 500 ps Typical Propagation Delays  
• PECL Mode Operating Range: V = 3.0 V to 5.5 V  
ORDERING INFORMATION  
CC  
with V = 0 V  
EE  
Device  
Package  
Shipping  
• NECL Mode Operating Range: V = 0 V  
CC  
MC10EP29DT  
TSSOP–20  
75 Units/Rail  
with V = –3.0 V to –5.5 V  
EE  
MC10EP29DTR2 TSSOP–20 2500 Tape & Reel  
MC100EP29DT TSSOP–20 75 Units/Rail  
• Open Input Default State  
• Safety Clamp on Inputs  
MC100EP29DTR2 TSSOP–20 2500 Tape & Reel  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
September, 2002 – Rev. 2  
MC10EP29/D  
12345678

中文翻译

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MC100EP29DT 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP29DTR2G ONSEMI

类似代替

 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DTG ONSEMI

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 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DTR2 ONSEMI

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 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset

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