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MC100EP29DTG

更新时间： 2024-11-05 04:17:35
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路光电二极管PC时钟
页数 文件大小 规格书
11页 173K
描述
3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

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中文翻译

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MC100EP29DTG 技术参数

是否无铅：不含铅生命周期：Active
零件包装代码：TSSOP包装说明：TSSOP, TSSOP20,.25
针数：20Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：1.66
Samacsys Confidence：3Samacsys Status：Released
Samacsys PartID：225068Samacsys Pin Count：20
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Small Outline Packages
Samacsys Footprint Name：TSSOP-20 CASE 948E-02 ISSUE CSamacsys Released Date：2015-08-06 09:29:15
Is Samacsys：N其他特性：NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
系列：100EJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：6.5 mm
逻辑集成电路类型：D FLIP-FLOP湿度敏感等级：1
位数：1功能数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：RAIL
峰值回流温度（摄氏度）：260电源：-4.5 V
最大电源电流（ICC）：60 mA传播延迟（tpd）：0.575 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：ECL
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

MC100EP29DTG 数据手册

 浏览型号MC100EP29DTG的Datasheet PDF文件第2页浏览型号MC100EP29DTG的Datasheet PDF文件第3页浏览型号MC100EP29DTG的Datasheet PDF文件第4页浏览型号MC100EP29DTG的Datasheet PDF文件第5页浏览型号MC100EP29DTG的Datasheet PDF文件第6页浏览型号MC100EP29DTG的Datasheet PDF文件第7页 
MC10EP29, MC100EP29  
3.3V / 5VꢀECL Dual  
Differential Data and Clock  
D Flip−Flop With Set and  
Reset  
http://onsemi.com  
MARKING  
Description  
The MC10/100EP29 is a dual master−slave flip−flop. The device  
features fully differential Data and Clock inputs as well as outputs.  
The MC10/100EP29 is functionally equivalent to the  
MC10/100EL29. Data enters the master latch when the clock is LOW  
and transfers to the slave upon a positive transition on the clock input.  
The differential inputs have special circuitry which ensures device  
stability under open input conditions. When both differential inputs  
DIAGRAM*  
XXXX  
EP29  
ALYWG  
G
are left open the D input will pull down to V and the D input will  
EE  
TSSOP−20  
DT SUFFIX  
CASE 948E  
bias around V /2. The outputs will go to a defined state, however the  
CC  
state will be random based on how the flip flop powers up.  
Both flip flops feature asynchronous, overriding Set and Reset  
inputs. Note that the Set and Reset inputs cannot both be HIGH  
simultaneously.  
20  
1
XXXX  
EP29  
ALYWG  
G
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
QFN−20  
differential input is connected to V as a switching reference voltage.  
MN SUFFIX  
CASE 485E  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
The 100 Series contains temperature compensation.  
xxx  
A
L
= MC10 or 100  
= Assembly Location  
= Wafer Lot  
BB  
Y
= Year  
= Work Week  
= Pb−Free Package  
Features  
W
G
• Maximum Frequency > 3 GHz Typical  
• 500 ps Typical Propagation Delays  
(Note: Microdot may be in either location)  
• PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
*For additional marking information, refer to  
Application Note AND8002/D.  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
CC  
with V = −3.0 V to −5.5 V  
EE  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
• Open Input Default State  
• Safety Clamp on Inputs  
• These are Pb−Free Devices  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 − Rev. 4  
MC10EP29/D  
1234567...11

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MC100EP29DTG 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP29MNG ONSEMI

完全替代

 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DTR2G ONSEMI

类似代替

 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DT ONSEMI

类似代替

 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset

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