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MC100EP31DT PDF预览

MC100EP31DT

更新时间: 2024-11-05 23:01:31
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
8页 76K
描述
D Flip Flop with Set and Reset

MC100EP31DT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, TSSOP-8
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.52其他特性:NECL MODE: VCC = 0V WITH VEE = -3.0V TO -5.5V
系列:100EJESD-30 代码:S-PDSO-G8
JESD-609代码:e0长度:3 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:3000000000 Hz
湿度敏感等级:1位数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:RAIL峰值回流温度(摄氏度):240
电源:-4.5 V最大电源电流(ICC):47 mA
传播延迟(tpd):0.41 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3 mmBase Number Matches:1

MC100EP31DT 数据手册

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MC10EP31, MC100EP31  
3.3V / 5VĄECL D Flip-Flop  
with Set and Reset  
The MC10/100EP31 is a D flip–flop with set and reset. The device  
is pin and functionally equivalent to the EL31 and LVEL31 devices.  
With AC performance much faster than the EL31 and LVEL31  
devices, the EP31 is ideal for applications requiring the fastest AC  
performance available. Both set and reset inputs are asynchronous,  
level triggered signals. Data enters the master portion of the flip–flop  
when CLK is low and is transferred to the slave, and thus the outputs,  
upon a positive transition of the CLK.  
http://onsemi.com  
MARKING DIAGRAMS*  
8
8
8
HEP31  
ALYW  
KEP31  
ALYW  
The 100 Series contains temperature compensation.  
1
SO–8  
340 ps Typical Propagation Delay  
Maximum Frequency > 3 GHz Typical  
D SUFFIX  
CASE 751  
1
1
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
8
1
8
1
8
NECL Mode Operating Range: V = 0 V  
CC  
1
HP31  
ALYW  
KP31  
ALYW  
with V = –3.0 V to –5.5 V  
EE  
TSSOP–8  
DT SUFFIX  
CASE 948R  
Open Input Default State  
Q Output Will Default LOW with Inputs Open or at V  
EE  
L = Wafer Lot  
Y = Year  
H = MC10  
K = MC100  
W = Work Week  
A = Assembly Location  
*For additional information, see Application Note  
AND8002/D  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10EP31D  
SO–8  
98 Units/Rail  
MC10EP31DR2  
MC100EP31D  
MC100EP31DR2  
MC10EP31DT  
SO–8  
SO–8  
2500 Tape & Reel  
98 Units/Rail  
SO–8  
2500 Tape & Reel  
100 Units/Rail  
TSSOP–8  
MC10EP31DTR2 TSSOP–8 2500 Tape & Reel  
MC100EP31DT TSSOP–8 100 Units/Rail  
MC100EP31DTR2 TSSOP–8 2500 Tape & Reel  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
April, 2001 – Rev. 5  
MC10EP31/D  

MC100EP31DT 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP35DT ONSEMI

完全替代

IC 100E SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, PLASTI
MC100LVEL31DTG ONSEMI

类似代替

3.3V ECL D Flip-Flop with Set and Reset
MC100EP31DTG ONSEMI

类似代替

3.3V / 5V ECL D Flip−Flop with Set and Reset

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