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MC100EP29MNG PDF预览

MC100EP29MNG

更新时间: 2024-11-05 03:15:11
品牌 Logo 应用领域
安森美 - ONSEMI 触发器时钟
页数 文件大小 规格书
11页 173K
描述
3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

MC100EP29MNG 数据手册

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MC10EP29, MC100EP29  
3.3V / 5VꢀECL Dual  
Differential Data and Clock  
D Flip−Flop With Set and  
Reset  
http://onsemi.com  
MARKING  
Description  
The MC10/100EP29 is a dual masterslave flipflop. The device  
features fully differential Data and Clock inputs as well as outputs.  
The MC10/100EP29 is functionally equivalent to the  
MC10/100EL29. Data enters the master latch when the clock is LOW  
and transfers to the slave upon a positive transition on the clock input.  
The differential inputs have special circuitry which ensures device  
stability under open input conditions. When both differential inputs  
DIAGRAM*  
XXXX  
EP29  
ALYWG  
G
are left open the D input will pull down to V and the D input will  
EE  
TSSOP20  
DT SUFFIX  
CASE 948E  
bias around V /2. The outputs will go to a defined state, however the  
CC  
state will be random based on how the flip flop powers up.  
Both flip flops feature asynchronous, overriding Set and Reset  
inputs. Note that the Set and Reset inputs cannot both be HIGH  
simultaneously.  
20  
1
XXXX  
EP29  
ALYWG  
G
The V pin, an internally generated voltage supply, is available to  
BB  
this device only. For single-ended input conditions, the unused  
QFN20  
differential input is connected to V as a switching reference voltage.  
MN SUFFIX  
CASE 485E  
BB  
V
BB  
may also rebias AC coupled inputs. When used, decouple V  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
to 0.5 mA. When not used, V should be left open.  
The 100 Series contains temperature compensation.  
xxx  
A
L
= MC10 or 100  
= Assembly Location  
= Wafer Lot  
BB  
Y
= Year  
= Work Week  
= PbFree Package  
Features  
W
G
Maximum Frequency > 3 GHz Typical  
500 ps Typical Propagation Delays  
(Note: Microdot may be in either location)  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
*For additional marking information, refer to  
Application Note AND8002/D.  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = 3.0 V to 5.5 V  
EE  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
Open Input Default State  
Safety Clamp on Inputs  
These are PbFree Devices  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 4  
MC10EP29/D  

MC100EP29MNG 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP29MNTXG ONSEMI

完全替代

3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DTR2G ONSEMI

完全替代

3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DTG ONSEMI

完全替代

3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

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