MC100EP29MNG

更新时间： 2024-11-21 03:15:11

品牌	Logo	应用领域
安森美 - ONSEMI		触发器时钟
页数	文件大小	规格书
11页	173K
描述
3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

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中文翻译

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替代型号

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MC100EP29MNG 数据手册

MC10EP29, MC100EP29

3.3V / 5VꢀECL Dual

Differential Data and Clock

D Flip−Flop With Set and

Reset

http://onsemi.com

MARKING

Description

The MC10/100EP29 is a dual master−slave flip−flop. The device

features fully differential Data and Clock inputs as well as outputs.

The MC10/100EP29 is functionally equivalent to the

MC10/100EL29. Data enters the master latch when the clock is LOW

and transfers to the slave upon a positive transition on the clock input.

The differential inputs have special circuitry which ensures device

stability under open input conditions. When both differential inputs

DIAGRAM*

XXXX

EP29

ALYWG

are left open the D input will pull down to V and the D input will

TSSOP−20

DT SUFFIX

CASE 948E

bias around V /2. The outputs will go to a defined state, however the

state will be random based on how the flip flop powers up.

Both flip flops feature asynchronous, overriding Set and Reset

inputs. Note that the Set and Reset inputs cannot both be HIGH

simultaneously.

XXXX

EP29

ALYWG

The V pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

QFN−20

differential input is connected to V as a switching reference voltage.

MN SUFFIX

CASE 485E

may also rebias AC coupled inputs. When used, decouple V

and V via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V should be left open.

The 100 Series contains temperature compensation.

xxx

= MC10 or 100

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Features

• Maximum Frequency > 3 GHz Typical

• 500 ps Typical Propagation Delays

(Note: Microdot may be in either location)

• PECL Mode Operating Range: V = 3.0 V to 5.5 V

*For additional marking information, refer to

Application Note AND8002/D.

with V = 0 V

• NECL Mode Operating Range: V = 0 V

with V = −3.0 V to −5.5 V

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

• Open Input Default State

• Safety Clamp on Inputs

• These are Pb−Free Devices

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

December, 2006 − Rev. 4

MC10EP29/D

12 3 4 5 6 7...11

中文翻译

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MC100EP29MNG 替代型号

型号	品牌	替代类型	描述	数据表
MC100EP29MNTXG	ONSEMI	完全替代	3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DTR2G	ONSEMI	完全替代	3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DTG	ONSEMI	完全替代	3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset

与MC100EP29MNG相关器件

型号	品牌	获取价格	描述	数据表
MC100EP29MNTXG	ONSEMI	获取价格	3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP31	ONSEMI	获取价格	3.3V / 5V ECL D Flip−Flop with Set and Reset
MC100EP31D	ONSEMI	获取价格	D Flip Flop with Set and Reset
MC100EP31DG	ONSEMI	获取价格	3.3V / 5V ECL D Flip−Flop with Set and Reset
MC100EP31DR2	ONSEMI	获取价格	D Flip Flop with Set and Reset
MC100EP31DR2G	ONSEMI	获取价格	3.3V / 5V ECL D Flip−Flop with Set and Reset
MC100EP31DT	ONSEMI	获取价格	D Flip Flop with Set and Reset
MC100EP31DTG	ONSEMI	获取价格	3.3V / 5V ECL D Flip−Flop with Set and Reset
MC100EP31DTR2	ONSEMI	获取价格	D Flip Flop with Set and Reset
MC100EP31DTR2G	ONSEMI	获取价格	3.3V / 5V ECL D Flip−Flop with Set and Reset

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