MC100EP31MNR4

更新时间： 2024-11-06 05:22:27

品牌	Logo	应用领域
安森美 - ONSEMI		触发器
页数	文件大小	规格书
11页	159K
描述
3.3V / 5V ECL D Flip−Flop with Set and Reset

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数据手册

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MC100EP31MNR4 数据手册

MC10EP31, MC100EP31

3.3V / 5VꢀECL D Flip−Flop

with Set and Reset

Description

The MC10/100EP31 is a D flip−flop with set and reset. The device

is pin and functionally equivalent to the EL31 and LVEL31 devices.

With AC performance much faster than the EL31 and LVEL31

devices, the EP31 is ideal for applications requiring the fastest AC

performance available. Both set and reset inputs are asynchronous,

level triggered signals. Data enters the master portion of the flip−flop

when CLK is low and is transferred to the slave, and thus the outputs,

upon a positive transition of the CLK.

http://onsemi.com

MARKING DIAGRAMS*

HEP31

ALYW

KEP31

ALYW

SOIC−8

D SUFFIX

CASE 751

Features

The 100 Series contains temperature compensation.

• 340 ps Typical Propagation Delay

• Maximum Frequency > 3 GHz Typical

• PECL Mode Operating Range:

HP31

KP31

= 3.0 V to 5.5 V with V = 0 V

ALYWG

TSSOP−8

DT SUFFIX

CASE 948R

• NECL Mode Operating Range:

= 0 V with V = −3.0 V to −5.5 V

• Open Input Default State

• Q Output Will Default LOW with Inputs Open or at V

• Pb−Free Packages are Available

DFN8

MN SUFFIX

CASE 506AA

= MC10

= MC100

= Assembly Location

= Wafer Lot

5O = MC10

3J = MC100

= Year

= Work Week

= Pb−Free Package

= Date Code

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

Publication Order Number:

December, 2006 − Rev. 9

MC10EP31/D

12 3 4 5 6 7...11

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MC100EP32DTG	ONSEMI	获取价格	3.3V / 5V ECL ±2 Divider
MC100EP32DTR2	ONSEMI	获取价格	3.3V 5V ECL / 2 Divider
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