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MC100EP32DG PDF预览

MC100EP32DG

更新时间: 2024-11-06 05:22:27
品牌 Logo 应用领域
安森美 - ONSEMI 预分频器多谐振动器逻辑集成电路光电二极管PC时钟
页数 文件大小 规格书
11页 165K
描述
3.3V / 5V ECL ±2 Divider

MC100EP32DG 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.51Samacsys Confidence:
Samacsys Status:ReleasedSamacsys PartID:411499
Samacsys Pin Count:8Samacsys Part Category:Integrated Circuit
Samacsys Package Category:OtherSamacsys Footprint Name:SOIC127P600X175-8N
Samacsys Released Date:2017-01-11 21:28:31Is Samacsys:N
其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V系列:100E
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm逻辑集成电路类型:PRESCALER
最大频率@ Nom-Sup:4000000000 Hz湿度敏感等级:1
数据/时钟输入次数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:-4.5 V最大电源电流(ICC):40 mA
传播延迟(tpd):0.45 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Prescaler/Multivibrators
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
Base Number Matches:1

MC100EP32DG 数据手册

 浏览型号MC100EP32DG的Datasheet PDF文件第2页浏览型号MC100EP32DG的Datasheet PDF文件第3页浏览型号MC100EP32DG的Datasheet PDF文件第4页浏览型号MC100EP32DG的Datasheet PDF文件第5页浏览型号MC100EP32DG的Datasheet PDF文件第6页浏览型号MC100EP32DG的Datasheet PDF文件第7页 
MC10EP32, MC100EP32  
3.3V / 5VꢀECL B2 Divider  
Description  
The MC10/100EP32 is an integrated B2 divider with differential  
CLK inputs.  
The V pin, an internally generated voltage supply, is available to  
this device only. For singleended input conditions, the unused  
BB  
http://onsemi.com  
MARKING DIAGRAMS*  
differential input is connected to V as a switching reference voltage.  
BB  
V
may also rebias AC coupled inputs. When used, decouple V  
BB  
BB  
and V via a 0.01 mF capacitor and limit current sourcing or sinking  
CC  
8
8
to 0.5 mA. When not used, V should be left open.  
BB  
8
HEP32  
ALYW  
G
KEP32  
ALYW  
G
The reset pin is asynchronous and is asserted on the rising edge.  
Upon powerup, the internal flipflops will attain a random state; the  
reset allows for the synchronization of multiple EP32’s in a system.  
The 100 Series contains temperature compensation.  
1
SOIC8  
D SUFFIX  
CASE 751  
1
1
Features  
350 ps Typical Propagation Delay  
Maximum Frequency > 4 GHz Typical (Figure 3)  
8
8
1
8
1
HP32  
KP32  
PECL Mode Operating Range:  
ALYWG  
ALYWG  
TSSOP8  
DT SUFFIX  
CASE 948R  
V
CC  
= 3.0 V to 5.5 V with V = 0 V  
G
G
EE  
1
NECL Mode Operating Range:  
= 0 V with V = 3.0 V to 5.5 V  
V
CC  
EE  
Open Input Default State  
Safety Clamp on Inputs  
Q Output Will Default LOW with Inputs Open or at V  
PbFree Packages are Available  
EE  
1
4
1
4
DFN8  
MN SUFFIX  
CASE 506AA  
H
K
= MC10  
= MC100  
A
L
= Assembly Location  
= Wafer Lot  
5P = MC10  
3K = MC100  
Y
W
G
= Year  
= Work Week  
= PbFree Package  
M
= Date Code  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 10  
MC10EP32/D  

MC100EP32DG 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP32DTR2G ONSEMI

完全替代

3.3V / 5V ECL ±2 Divider
MC100EP32DR2G ONSEMI

完全替代

3.3V / 5V ECL ±2 Divider
MC10EP32DR2G ONSEMI

完全替代

3.3V / 5V ECL ±2 Divider

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