Datasheet > MC100EP223TC

MC100EP223TC

更新时间： 2024-09-15 11:10:59

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		时钟驱动器逻辑集成电路
页数	文件大小	规格书
8页	87K
描述
Low-Voltage 1:22 Differential PECL/HSTL Clock Driver

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MC100EP223TC 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC100EP223 is a low skew 1–to–22 differential driver, designed

with clock distribution in mind. It accepts two clock sources into an input

multiplexer. The selected signal is fanned out to 22 identical differential

outputs.

LOW–VOLTAGE

1:22 DIFFERENTIAL

PECL/HSTL CLOCK DRIVER

•

200ps Part–to–Part Skew

50ps Output–to–Output Skew

Differential Design

Open Emitter HSTL Compatible Outputs

3.3V V

Both PECL and HSTL Inputs

75kΩ Input Pulldown Resistors

Thermally Enhanced 64 lead Exposed Pad LQFP

The EP223 is specifically designed, modeled and produced with low

skew as the key goal. Optimal design and layout serve to minimize

gate–to–gate skew within a device, and empirical modeling is used to

determine process control limits that ensure consistent t distributions

from lot to lot. The net result is a dependable, guaranteed low skew

device.

TC SUFFIX

64–LEAD LQFP PACKAGE

CASE 840K–01

The EP223 HSTL outputs are not realized in the conventional

manner. To minimize part–to–part and output–to–output skew, the HSTL

compatible output levels are generated with an open emitter

architecture. The outputs are pulled down with 50Ω to ground, rather

than the typical 50Ω to V

pullup of a “standard” HSTL output.

DDQ

Because the HSTL outputs are pulled to ground, the EP223 does not

utilize the V supply of the HSTL standard. The output levels are

DDQ

derived from V

In the case of an asynchronous control, there is a chance of

generating a ‘runt’ clock pulse when the device is enabled/disabled. To

avoid this, the output enable (OE) is synchronous so that the outputs

will only be enabled/disabled when they are already in the LOW state.

To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into

50Ω, even if only one side is being used. In most applications, all 22 differential pairs will be used and therefore terminated. In

the case where fewer than 22 pairs are used, it is necessary to terminate at least the output pairs on the same package side as

the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of

propagation delay (on the order of 10–20ps) of the output(s) being used which, while not being catastrophic to most designs, will

mean a loss of skew margin.

This document contains information on a product under development. Motorola reserves the right to change or

discontinue this product without notice.

03/01

REV 2

Motorola, Inc. 2001

12 3 4 5 6 7 8

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与MC100EP223TC相关器件

型号	品牌	获取价格	描述	数据表
MC100EP29	ONSEMI	获取价格	3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DT	ONSEMI	获取价格	3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
MC100EP29DTG	ONSEMI	获取价格	3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29DTR2	ONSEMI	获取价格	3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
MC100EP29DTR2G	ONSEMI	获取价格	3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29MNG	ONSEMI	获取价格	3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP29MNTXG	ONSEMI	获取价格	3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
MC100EP31	ONSEMI	获取价格	3.3V / 5V ECL D Flip−Flop with Set and Reset
MC100EP31D	ONSEMI	获取价格	D Flip Flop with Set and Reset
MC100EP31DG	ONSEMI	获取价格	3.3V / 5V ECL D Flip−Flop with Set and Reset

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