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M74HCT74B1R PDF预览

M74HCT74B1R

更新时间: 2024-09-16 23:01:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
10页 435K
描述
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR

M74HCT74B1R 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-14
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.84
Is Samacsys:N系列:HCT
JESD-30 代码:R-PDIP-T14JESD-609代码:e3
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:18000000 Hz最大I(ol):0.004 A
位数:1功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):50 ns认证状态:Not Qualified
座面最大高度:5.1 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Matte Tin (Sn)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:18 MHz
Base Number Matches:1

M74HCT74B1R 数据手册

 浏览型号M74HCT74B1R的Datasheet PDF文件第2页浏览型号M74HCT74B1R的Datasheet PDF文件第3页浏览型号M74HCT74B1R的Datasheet PDF文件第4页浏览型号M74HCT74B1R的Datasheet PDF文件第5页浏览型号M74HCT74B1R的Datasheet PDF文件第6页浏览型号M74HCT74B1R的Datasheet PDF文件第7页 
M74HCT74  
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED :  
= 48MHz (TYP.) at V = 4.5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 74  
TUBE  
DIP  
SOP  
M74HCT74B1R  
M74HCT74M1R  
M74HCT74RM13TR  
M74HCT74TTR  
DESCRIPTION  
The M74HCT74 is an high speed CMOS DUAL D  
TYPE FLIP FLOP WITH CLEAR fabricated with  
TSSOP  
2
silicon gate C MOS technology.  
The M74HCT74 is designed to directly interface  
HSC MOS systems with TTL and NMOS  
components.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
A signal on the D INPUT (nD) is transferred on the  
Q OUTPUT during the positive going transition of  
the clock pulse. CLEAR (CLR) and PRESET (PR)  
are independent of the clock and accomplished by  
a low on the appropriate input.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/10  

M74HCT74B1R 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT74M TI

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Dual D Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HCT74E TI

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Dual D Flip-Flop with Set and Reset Positive-Edge Trigger
SN74HCT74N TI

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DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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