M74HCT75C1R

更新时间： 2024-11-22 23:01:27

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		锁存器
页数	文件大小	规格书
9页	241K
描述
4 BIT D TYPE LATCH

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中文翻译

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数据手册

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M74HCT75C1R 数据手册

M54HCT75

M74HCT75

4 BIT D TYPE LATCH

HIGH SPEED

t_PD= 15 ns (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 2 µA (MAX.) AT T_A= 25 °C

COMPATIBLE WITH TTL OUTPUTS

V_IH= 2 V (MIN.) V_IL= 0.8 V (MAX.)

OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

IOH = I_OL= 4 mA (MIN.)

B1R

(Plastic Package)

F1R

(Ceramic Package)

PIN AND FUNCTION COMPATIBLE WITH

54/74LS75

M1R

(Micro Package)

C1R

(Chip Carrier)

DESCRIPTION

TheM54/74HCT75 isahigh speedCMOS4-BITD-TYPE

LATCH fabricated in silicon gate C2MOS technology. It

has the same high speed performance of LSTTL com-

bined withtrue CMOS low power consumption. It contains

two groups of 2-bit latches controlled by an enable input

(G1 • 2 or G3 • 4). These two latch groups can be used

indifferent circuits. Each latch has Q and Q outputs (1Q -

4Q and 1Q - 4Q). The data applied to the data input is

transfered to the Q and Q outputs when the enable input

is taken high and the outputs will follow the data input as

long as the enable input is kept high. When the enable

input is taken low, the information data applied to the data

input is retained at the outputs. All inputs are equipped with

protection circuits against static discharge and transient

excessvoltage.This integrated circuit has input andoutput

characteristics that are fully compatible with 54/74 LSTTL

logic families. M54/74HCT devices are designed to di-

rectly interface HSC²MOS systemswith TTL and NMOS

components. They are also plug in replacements for

LSTTL devices giving a reduction of power consumption.

ORDER CODES :

M54HCT75F1R

M74HCT75M1R

M74HCT75B1R

M74HCT75C1R

PIN CONNECTIONS (top view)

INPUT AND OUTPUT EQUIVALENT CIRCUIT

NC =

No Internal

Connection

January 1993

1/9

12 3 4 5 6 7...9

中文翻译

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