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M74HCT75RM13TR PDF预览

M74HCT75RM13TR

更新时间: 2024-11-22 23:01:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 283K
描述
4 BIT D TYPE LATCH

M74HCT75RM13TR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.71Is Samacsys:N
系列:HCTJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:D LATCH
最大I(ol):0.004 A位数:2
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:42 ns
传播延迟(tpd):50 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:HIGH LEVEL
宽度:3.9 mmBase Number Matches:1

M74HCT75RM13TR 数据手册

 浏览型号M74HCT75RM13TR的Datasheet PDF文件第2页浏览型号M74HCT75RM13TR的Datasheet PDF文件第3页浏览型号M74HCT75RM13TR的Datasheet PDF文件第4页浏览型号M74HCT75RM13TR的Datasheet PDF文件第5页浏览型号M74HCT75RM13TR的Datasheet PDF文件第6页浏览型号M74HCT75RM13TR的Datasheet PDF文件第7页 
M74HCT75  
4 BIT D TYPE LATCH  
HIGH SPEED :  
= 21ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 75  
TUBE  
DIP  
SOP  
M74HCT75B1R  
M74HCT75M1R  
M74HCT75RM13TR  
M74HCT75TTR  
DESCRIPTION  
The M74HCT75 is an high speed CMOS 4 BIT D  
TYPE LATCH fabricated with silicon gate C MOS  
TSSOP  
2
technology.  
enable input is taken low, the information data  
applied to the data input is retained at the outputs.  
The M74HCT75 is designed to directly interface  
HSC MOS systems with TTL and NMOS  
components.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
It contains two groups of 2 bit latches controlled by  
an enable input (G12 or G34). These two latch  
groups can be used in different circuits. Each latch  
has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The  
data applied to the data input is transferred to the  
Q and Q outputs when the enable input is taken  
high and the outputs will follow the data input as  
long as the enable input is kept high. When the  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
September 2001  
1/9  

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