CD74HCT74M

更新时间： 2024-11-10 23:04:31

品牌	Logo	应用领域
德州仪器 - TI		触发器逻辑集成电路光电二极管
页数	文件大小	规格书
8页	45K
描述
Dual D Flip-Flop with Set and Reset Positive-Edge Trigger

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中文翻译

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数据手册
替代型号

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CD74HCT74M 数据手册

CD54HC74, CD74HC74,

CD74HCT74

Data sheet acquired from Harris Semiconductor

SCHS124

Dual D Flip-Flop with Set and Reset

Positive-Edge Trigger

January 1998

Features

Description

• Hysteresis on Clock Inputs for Improved Noise Immu-

nity and Increased Input Rise and Fall Times

The Harris CD54HC74, CD74HC74 and CD74HCT74 utilize

silicon gate CMOS technology to achieve operating speeds

equivalent to LSTTL parts. They exhibit the low power

consumption of standard CMOS integrated circuits, together

with the ability to drive 10 LSTTL loads.

[ /Title

(CD54H

C74,

CD74H

C74,

CD74H

CT74)

/Subject

(Dual D

Flip-

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

This ﬂip-ﬂop has independent DATA, SET, RESET and

CLOCK inputs and Q and Q outputs. The logic level present

at the data input is transferred to the output during the

positive-going transition of the clock pulse. SET and RESET

are independent of the clock and are accomplished by a low

level at the appropriate input.

• Typical f

MAX

= 50MHz at V = 5V, C = 15pF,

CC L

T = 25 C

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The 74HCT logic family is functionally as well as pin

compatible with the standard 74LS logic family.

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

Flop

with Set

Ordering Information

TEMP. RANGE

PKG.

NO.

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

PART NUMBER

CD54HC74F

CD74HC74E

CD74HCT74E

CD74HC74M

CD74HCT74M

NOTES:

( C)

PACKAGE

-55 to 125

14 Ld CERDIP F14.3

• HC Types

14 Ld PDIP

14 Ld SOIC

E14.3

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

E14.3

at V

= 5V

M14.15

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

2. Die is available which meets all electrical specifications. Please

contact your local sales office or Harris customer service for

ordering information.

Pinout

CD54HC74, CD74HC74, CD74HCT74

(PDIP, SOIC, CERDIP)

TOP VIEW

14 V

13 2R

12 2D

11 2CP

10 2S

1CP

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1476.1

12 3 4 5 6 7 8

中文翻译

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CD74HCT74M 替代型号

型号	品牌	替代类型	描述	数据表
CD74HCT74M96G4	TI	完全替代	具有设置和复位端的高速 CMOS 逻辑双路正边沿触发式 D 触发器 \| D \| 14 \|
CD74HCT74E	TI	完全替代	Dual D Flip-Flop with Set and Reset Positive-Edge Trigger
SN74HCT74D	TI	类似代替	DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

与CD74HCT74M相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT74M96	TI	获取价格	Dual D Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HCT74M96	ROCHESTER	获取价格	D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO
CD74HCT74M96E4	ROCHESTER	获取价格	D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO
CD74HCT74M96E4	TI	获取价格	HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN,
CD74HCT74M96G4	TI	获取价格	具有设置和复位端的高速 CMOS 逻辑双路正边沿触发式 D 触发器 \| D \| 14 \|
CD74HCT74MG4	TI	获取价格	HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN,
CD74HCT74MT	TI	获取价格	Dual D Flip-Flop with Set and Reset Positive-Edge Trigger
CD74HCT74MTG4	TI	获取价格	HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN,
CD74HCT75	TI	获取价格	Dual 2-Bit Bistable Transparent Latch
CD74HCT75E	TI	获取价格	Dual 2-Bit Bistable Transparent Latch

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