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CD74HCT74M96E4 PDF预览

CD74HCT74M96E4

更新时间： 2024-11-11 19:25:35
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
17页 620K
描述
D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14

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CD74HCT74M96E4 技术参数

生命周期：Contact Manufacturer包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.62系列：HCT
JESD-30 代码：R-PDSO-G14长度：8.65 mm
逻辑集成电路类型：D FLIP-FLOP位数：1
功能数量：2端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE传播延迟（tpd）：53 ns
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：3.9 mm
最小 fmax：16 MHzBase Number Matches：1

CD74HCT74M96E4 数据手册

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CD54HC74, CD74HC74,  
CD54HCT74, CD74HCT74  
Data sheet acquired from Harris Semiconductor  
SCHS124D  
Dual D Flip-Flop with Set and Reset  
Positive-Edge Trigger  
January 1998 - Revised September 2003  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise The ’HC74 and ’HCT74 utilize silicon gate CMOS technology  
Immunity and Increased Input Rise and Fall Times  
• Asynchronous Set and Reset  
• Complementary Outputs  
to achieve operating speeds equivalent to LSTTL parts.  
They exhibit the low power consumption of standard CMOS  
integrated circuits, together with the ability to drive 10 LSTTL  
loads.  
[ /Title  
(CD54H  
C74,  
CD74H  
C74,  
This flip-flop has independent DATA, SET, RESET and  
CLOCK inputs and Q and Q outputs. The logic level present  
at the data input is transferred to the output during the  
positive-going transition of the clock pulse. SET and RESET  
are independent of the clock and are accomplished by a low  
level at the appropriate input.  
• Buffered Inputs  
• Typical f  
MAX  
= 50MHz at V = 5V, C = 15pF,  
CC L  
o
CD74H  
CT74)  
/Subject  
(Dual D  
Flip-  
T = 25 C  
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible  
with the standard LS logic family.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Flop  
with Set  
Ordering Information  
TEMP. RANGE  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
o
PART NUMBER  
CD54HC74F3A  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
CD54HCT74F3A  
CD74HC74E  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
IL  
IH  
at V  
= 5V  
CC  
CD74HC74M  
• HCT Types  
CD74HC74MT  
CD74HC74M96  
CD74HCT74E  
CD74HCT74M  
CD74HCT74MT  
CD74HCT74M96  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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