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SN74HCT74D PDF预览

SN74HCT74D

更新时间: 2024-02-08 23:46:38
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管PC
页数 文件大小 规格书
5页 103K
描述
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

SN74HCT74D 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.13
系列:HCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:22000000 Hz最大I(ol):0.004 A
湿度敏感等级:1位数:1
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:35 ns传播延迟(tpd):35 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:24 MHzBase Number Matches:1

SN74HCT74D 数据手册

 浏览型号SN74HCT74D的Datasheet PDF文件第2页浏览型号SN74HCT74D的Datasheet PDF文件第3页浏览型号SN74HCT74D的Datasheet PDF文件第4页浏览型号SN74HCT74D的Datasheet PDF文件第5页 
SN54HCT74, SN74HCT74  
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCLS169B – DECEMBER 1982 – REVISED MAY 1997  
SN54HCT74 . . . J OR W PACKAGE  
SN74HCT74 . . . D, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Package Options Include Plastic  
Small-Outline (D), Thin Shrink  
Small-Outline (PW), and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
1CLK  
1PRE  
1Q  
2CLK  
10 2PRE  
description  
9
8
1Q  
2Q  
2Q  
The ’HCT74 contain two independent D-type  
positive-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the data (D) input meeting the setup  
time requirements are transferred to the outputs  
on the positive-going edge of the clock (CLK)  
pulse. Clock triggering occurs at a voltage level  
and is not directly related to the rise time of CLK.  
Following the hold-time interval, data at the  
D input may be changed without affecting the  
levels at the outputs.  
GND  
SN54HCT74 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2D  
1CLK  
NC  
4
5
6
7
8
NC  
17  
16  
2CLK  
1PRE  
NC  
15 NC  
14  
9 10 11 12 13  
2PRE  
1Q  
The SN54HCT74 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HCT74 is characterized for  
operation from –40°C to 85°C.  
NC – No internal connection  
FUNCTION TABLE  
INPUTS  
OUTPUT  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
H
L
L
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q
Q
0
0
This configuration is unstable; that is, it does not  
persist when PRE or CLR returns to its inactive  
(high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74HCT74D 替代型号

型号 品牌 替代类型 描述 数据表
SN74HCT74DRG4 TI

完全替代

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HCT74DRE4 TI

完全替代

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HCT74DG4 TI

完全替代

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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