CD74HCT74E

更新时间： 2024-02-23 05:37:02

品牌	Logo	应用领域
德州仪器 - TI		触发器锁存器
页数	文件大小	规格书
8页	45K
描述
Dual D Flip-Flop with Set and Reset Positive-Edge Trigger

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技术参数
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CD74HCT74E 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP14,.25	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e0	负载电容（CL）：	50 pF
逻辑集成电路类型：	D FLIP-FLOP	最大频率@ Nom-Sup：	16000000 Hz
最大I（ol）：	0.004 A	功能数量：	2
端子数量：	14	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP14,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	5 V	子类别：	FF/Latches
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
触发器类型：	POSITIVE EDGE	Base Number Matches：	1

CD74HCT74E 数据手册

CD54HC74, CD74HC74,

CD74HCT74

Data sheet acquired from Harris Semiconductor

SCHS124

Dual D Flip-Flop with Set and Reset

Positive-Edge Trigger

January 1998

Features

Description

• Hysteresis on Clock Inputs for Improved Noise Immu-

nity and Increased Input Rise and Fall Times

The Harris CD54HC74, CD74HC74 and CD74HCT74 utilize

silicon gate CMOS technology to achieve operating speeds

equivalent to LSTTL parts. They exhibit the low power

consumption of standard CMOS integrated circuits, together

with the ability to drive 10 LSTTL loads.

[ /Title

(CD54H

C74,

CD74H

C74,

CD74H

CT74)

/Subject

(Dual D

Flip-

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

This ﬂip-ﬂop has independent DATA, SET, RESET and

CLOCK inputs and Q and Q outputs. The logic level present

at the data input is transferred to the output during the

positive-going transition of the clock pulse. SET and RESET

are independent of the clock and are accomplished by a low

level at the appropriate input.

• Typical f

MAX

= 50MHz at V = 5V, C = 15pF,

CC L

T = 25 C

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The 74HCT logic family is functionally as well as pin

compatible with the standard 74LS logic family.

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

Flop

with Set

Ordering Information

TEMP. RANGE

PKG.

NO.

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

PART NUMBER

CD54HC74F

CD74HC74E

CD74HCT74E

CD74HC74M

CD74HCT74M

NOTES:

( C)

PACKAGE

-55 to 125

14 Ld CERDIP F14.3

• HC Types

14 Ld PDIP

14 Ld SOIC

E14.3

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

E14.3

at V

= 5V

M14.15

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

2. Die is available which meets all electrical specifications. Please

contact your local sales office or Harris customer service for

ordering information.

Pinout

CD54HC74, CD74HC74, CD74HCT74

(PDIP, SOIC, CERDIP)

TOP VIEW

14 V

13 2R

12 2D

11 2CP

10 2S

1CP

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1476.1

12 3 4 5 6 7 8

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与CD74HCT74E相关器件

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CD74HCT74EE4	ROCHESTER	D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO	获取价格
CD74HCT74EN	ETC	Logic IC	获取价格
CD74HCT74EX	ROCHESTER	D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO	获取价格
CD74HCT74EX	RENESAS	IC,FLIP-FLOP,DUAL,D TYPE,HCT-CMOS,DIP,14PIN,PLASTIC	获取价格
CD74HCT74F	ETC	Logic IC	获取价格
CD74HCT74H	RENESAS	IC,FLIP-FLOP,DUAL,D TYPE,HCT-CMOS,DIE	获取价格

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