Datasheet > CD74HCT74EE4

CD74HCT74EE4

更新时间： 2024-01-18 15:13:42

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		光电二极管逻辑集成电路触发器
页数	文件大小	规格书
17页	620K
描述
D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14

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CD74HCT74EE4 技术参数

生命周期：	Contact Manufacturer	包装说明：	DIP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.62	系列：	HCT
JESD-30 代码：	R-PDIP-T14	长度：	19.305 mm
逻辑集成电路类型：	D FLIP-FLOP	位数：	1
功能数量：	2	端子数量：	14
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出极性：	COMPLEMENTARY	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	传播延迟（tpd）：	53 ns
座面最大高度：	5.08 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
触发器类型：	POSITIVE EDGE	宽度：	7.62 mm
最小 fmax：	16 MHz	Base Number Matches：	1

CD74HCT74EE4 数据手册

CD54HC74, CD74HC74,

CD54HCT74, CD74HCT74

Data sheet acquired from Harris Semiconductor

SCHS124D

Dual D Flip-Flop with Set and Reset

Positive-Edge Trigger

January 1998 - Revised September 2003

Features

Description

• Hysteresis on Clock Inputs for Improved Noise The ’HC74 and ’HCT74 utilize silicon gate CMOS technology

Immunity and Increased Input Rise and Fall Times

• Asynchronous Set and Reset

• Complementary Outputs

to achieve operating speeds equivalent to LSTTL parts.

They exhibit the low power consumption of standard CMOS

integrated circuits, together with the ability to drive 10 LSTTL

loads.

[ /Title

(CD54H

C74,

CD74H

C74,

This ﬂip-ﬂop has independent DATA, SET, RESET and

CLOCK inputs and Q and Q outputs. The logic level present

at the data input is transferred to the output during the

positive-going transition of the clock pulse. SET and RESET

are independent of the clock and are accomplished by a low

level at the appropriate input.

• Buffered Inputs

• Typical f

MAX

= 50MHz at V = 5V, C = 15pF,

CC L

CD74H

CT74)

/Subject

(Dual D

Flip-

T = 25 C

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible

with the standard LS logic family.

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

Flop

with Set

Ordering Information

TEMP. RANGE

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

PART NUMBER

CD54HC74F3A

( C)

PACKAGE

14 Ld CERDIP

14 Ld PDIP

14 Ld SOIC

14 Ld PDIP

14 Ld SOIC

-55 to 125

• HC Types

CD54HCT74F3A

CD74HC74E

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

at V

= 5V

CD74HC74M

• HCT Types

CD74HC74MT

CD74HC74M96

CD74HCT74E

CD74HCT74M

CD74HCT74MT

CD74HCT74M96

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...17

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与CD74HCT74EE4相关器件

型号	品牌	描述	获取价格	数据表
CD74HCT74EN	ETC	Logic IC	获取价格
CD74HCT74EX	ROCHESTER	D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO	获取价格
CD74HCT74EX	RENESAS	IC,FLIP-FLOP,DUAL,D TYPE,HCT-CMOS,DIP,14PIN,PLASTIC	获取价格
CD74HCT74F	ETC	Logic IC	获取价格
CD74HCT74H	RENESAS	IC,FLIP-FLOP,DUAL,D TYPE,HCT-CMOS,DIE	获取价格
CD74HCT74M	RENESAS	D FLIP-FLOP	获取价格

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