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M74HCT74MTCX

更新时间： 2024-11-09 13:10:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 88K
描述
D Flip-Flop, HCT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, 4.40 MM, MO-153, TSSOP-14

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M74HCT74MTCX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP14,.25
针数：14Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.26
系列：HCTJESD-30 代码：R-PDSO-G14
长度：5 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：21000000 Hz
最大I（ol）：0.004 A位数：1
功能数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL电源：5 V
传播延迟（tpd）：44 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：50 MHz
Base Number Matches：1

M74HCT74MTCX 数据手册

 浏览型号M74HCT74MTCX的Datasheet PDF文件第2页浏览型号M74HCT74MTCX的Datasheet PDF文件第3页浏览型号M74HCT74MTCX的Datasheet PDF文件第4页浏览型号M74HCT74MTCX的Datasheet PDF文件第5页浏览型号M74HCT74MTCX的Datasheet PDF文件第6页浏览型号M74HCT74MTCX的Datasheet PDF文件第7页 
February 1984  
Revised January 1999  
MM74HCT74  
Dual D-Type Flip-Flop with Preset and Clear  
tected from damage due to static discharge by internal  
diode clamps to VCC and ground.  
General Description  
The MM74HCT74 utilizes advanced silicon-gate CMOS  
technology to achieve operation speeds similar to the  
equivalent LS-TTL part. It possesses the high noise immu-  
nity and low power consumption of standard CMOS inte-  
grated circuits, along with the ability to drive 10 LS-TTL  
loads.  
MM74HCT devices are intended to interface between TTL  
and NMOS components and standard CMOS devices.  
These parts are also plug-in replacements for LS-TTL  
devices and can be used to reduce power consumption in  
existing designs.  
This flip-flop has independent data, preset, clear, and clock  
inputs and Q and Q outputs. The logic level present at the  
data input is transferred to the output during the positive-  
going transition of the clock pulse. Preset and clear are  
independent of the clock and accomplished by a low level  
at the appropriate input.  
Features  
■ Typical propagation delay: 20 ns  
■ Low quiescent current: 40 µA maximum (74HCT Series)  
■ Low input current: 1 µA maximum  
■ Fanout of 10 LS-TTL loads  
The 74HCT logic family is functionally and pin-out compati-  
ble with the standard 74LS logic family. All inputs are pro-  
■ Meta-stable hardened  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HCT74M  
MM74HCT74SJ  
M74HCT74MTC  
MM74HCT74N  
M14A  
M14D  
MTC14  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Inputs  
Outputs  
PR  
L
CLR  
CLK  
X
D
X
X
X
Q
Q
L
H
L
L
H
L
H
X
H
L
X
H
H
(Note 1) (Note 1)  
H
H
H
H
H
H
↑
↑
L
H
L
H
L
L
H
X
Q0  
Q0  
Q0 = the level of Q before the indicated input conditions were established.  
Note 1: This configuration is nonstable; that is, it will not persist when pre-  
set and clear inputs return to their inactive (HIGH) level.  
© 1999 Fairchild Semiconductor Corporation  
DS005360.prf  
www.fairchildsemi.com  
1234567

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