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M74HCT75-2 PDF预览

M74HCT75-2

更新时间: 2024-11-22 23:01:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 锁存器
页数 文件大小 规格书
9页 283K
描述
4 BIT D TYPE LATCH

M74HCT75-2 数据手册

 浏览型号M74HCT75-2的Datasheet PDF文件第2页浏览型号M74HCT75-2的Datasheet PDF文件第3页浏览型号M74HCT75-2的Datasheet PDF文件第4页浏览型号M74HCT75-2的Datasheet PDF文件第5页浏览型号M74HCT75-2的Datasheet PDF文件第6页浏览型号M74HCT75-2的Datasheet PDF文件第7页 
M74HCT75  
4 BIT D TYPE LATCH  
HIGH SPEED :  
= 21ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 75  
TUBE  
DIP  
SOP  
M74HCT75B1R  
M74HCT75M1R  
M74HCT75RM13TR  
M74HCT75TTR  
DESCRIPTION  
The M74HCT75 is an high speed CMOS 4 BIT D  
TYPE LATCH fabricated with silicon gate C MOS  
TSSOP  
2
technology.  
enable input is taken low, the information data  
applied to the data input is retained at the outputs.  
The M74HCT75 is designed to directly interface  
HSC MOS systems with TTL and NMOS  
components.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
It contains two groups of 2 bit latches controlled by  
an enable input (G12 or G34). These two latch  
groups can be used in different circuits. Each latch  
has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The  
data applied to the data input is transferred to the  
Q and Q outputs when the enable input is taken  
high and the outputs will follow the data input as  
long as the enable input is kept high. When the  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
September 2001  
1/9  

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