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IS64VPS409618B-200B3LA3 PDF预览

IS64VPS409618B-200B3LA3

更新时间： 2024-11-05 19:27:55
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
39页 1276K
描述
Standard SRAM, 4MX18, 3.1ns, CMOS, PBGA165, 13 X 15 MM, LEAD FREE, PLASTIC, TFBGA-165

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IS64VPS409618B-200B3LA3 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：TBGA,Reach Compliance Code：compliant
风险等级：5.76最长访问时间：3.1 ns
JESD-30 代码：R-PBGA-B165JESD-609代码：e1
长度：15 mm内存密度：75497472 bit
内存集成电路类型：STANDARD SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：4194304 words
字数代码：4000000工作模式：SYNCHRONOUS
最高工作温度：125 °C最低工作温度：-40 °C
组织：4MX18封装主体材料：PLASTIC/EPOXY
封装代码：TBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260座面最大高度：1.2 mm
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：10宽度：13 mm
Base Number Matches：1

IS64VPS409618B-200B3LA3 数据手册

 浏览型号IS64VPS409618B-200B3LA3的Datasheet PDF文件第2页浏览型号IS64VPS409618B-200B3LA3的Datasheet PDF文件第3页浏览型号IS64VPS409618B-200B3LA3的Datasheet PDF文件第4页浏览型号IS64VPS409618B-200B3LA3的Datasheet PDF文件第5页浏览型号IS64VPS409618B-200B3LA3的Datasheet PDF文件第6页浏览型号IS64VPS409618B-200B3LA3的Datasheet PDF文件第7页 
wordsꢀbyꢀ32ꢀbits.  
                                                                   
36ꢀbits.ꢀTheꢀIS61LPS204832Bꢀisꢀorganizedꢀasꢀ2,096,952ꢀ  
TheꢀIS61LPS/VPS409618Bꢀisꢀorganizedꢀ  
                                                             
IS61LPS409618B, IS61LPS204836B, IS61LPS204832B, IS64LPS204836B,  
IS61VPS/VVPS409618B, IS61VPS/VVPS204836B  
2M x 36, 2M x 32, 4M x 18  
72 Mb SYNCHRONOUS PIPELINED,  
SEPTEMBER 2015  
SINgLE CYCLE DESELECT STATIC RAM  
FEATURES  
DESCRIPTION  
Theꢀ72Mbꢀproductꢀfamilyꢀfeaturesꢀ high-speed,ꢀlow-powerꢀ  
synchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀburstable,ꢀ  
high-performanceꢀ memoryꢀ forꢀ communicationꢀ andꢀ net-  
workingꢀapplications.ꢀTheꢀIS61LPS/VPS204836Bꢀandꢀ  
IS64LPS204836Bꢀareꢀorganizedꢀasꢀ2,096,952ꢀwordsꢀbyꢀ  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ  
control  
•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ  
asꢀ4,193,904ꢀwordsꢀbyꢀ18ꢀbits.ꢀFabricatedꢀwithꢀISSI'sꢀ  
advancedꢀ CMOSꢀ technology,ꢀ theꢀ deviceꢀ integratesꢀ aꢀ  
2-bitꢀburstꢀcounter,ꢀhigh-speedꢀSRAMꢀcore,ꢀandꢀhigh-  
driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀmonolithicꢀcircuit.ꢀAllꢀ  
synchronousꢀinputsꢀpassꢀthroughꢀregistersꢀcontrolledꢀbyꢀ  
aꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.  
•ꢀ Threeꢀchipꢀenableꢀoptionꢀforꢀsimpleꢀdepthꢀex-  
pansionꢀandꢀaddressꢀpipelining  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ AutoꢀPower-downꢀduringꢀdeselect  
•ꢀ Singleꢀcycleꢀdeselect  
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ  
theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀ  
oneꢀtoꢀfourꢀbytesꢀwideꢀasꢀcontrolledꢀbyꢀtheꢀwriteꢀcontrolꢀ  
inputs.  
•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby  
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackage  
•ꢀ PowerꢀSupply  
Separateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀwritten.ꢀ  
Theꢀbyteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀtheꢀbyteꢀ  
writeꢀenableꢀ(BWE)ꢀinputꢀcombinedꢀwithꢀoneꢀorꢀmoreꢀ  
individualꢀbyteꢀwriteꢀsignalsꢀ(BWx). Inꢀaddition,ꢀGlobalꢀ  
Writeꢀ(GW)ꢀisꢀavailableꢀforꢀwritingꢀallꢀbytesꢀatꢀoneꢀtime,ꢀ  
regardlessꢀofꢀtheꢀbyteꢀwriteꢀcontrols.  
ꢀ LPS:ꢀVdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)  
VPS:ꢀVdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)  
VVPS:ꢀVdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)  
•ꢀ JEDECꢀ100-PinꢀTQFP,ꢀ119-ballꢀPBGA,ꢀandꢀ  
165-ballꢀPBGAꢀpackages  
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSPꢀ(AddressꢀStatusꢀ  
Processor)ꢀorꢀADSCꢀ(AddressꢀStatusꢀCacheꢀController)ꢀ  
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-  
atedꢀinternallyꢀandꢀcontrolledꢀbyꢀtheꢀADVꢀ(burstꢀaddressꢀ  
advance)ꢀinputꢀpin.ꢀ  
•ꢀ Lead-freeꢀavailable  
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀor-  
der,ꢀLinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀ  
InterleaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀ  
orꢀleftꢀfloating.  
FAST ACCESS TIME  
Symbol  
tkq  
Parameter  
250  
2.8  
4
200  
3.1  
5
166  
Units  
ns  
Clock Access Time  
Cycle Time  
3.8  
6
tkc  
ns  
Frequency  
250  
200  
166  
MHz  
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause  
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written  
assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. C1  
9/15/2015  
1234567...39

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