Datasheet > IS61NVP6436A

IS61NVP6436A

更新时间： 2024-10-13 04:58:39

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
21页	130K
描述
64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM

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IS61NVP6436A 数据手册

IS61NLP6432A

IS61NLP6436A/IS61NVP6436A

IS61NLP12818A/IS61NVP12818A

64K x 32, 64K x 36, and 128K x 18

2Mb, PIPELINE 'NO WAIT' STATE BUS SRAM

ISSI

PRELIMINARYINFORMATION

SEPTEMBER 2005

FEATURES

DESCRIPTION

The 2 Meg 'NLP/NVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

networking and communications applications. They are

organized as 64K words by 32 bits, 64K words by 36 bits,

and128K wordsby18bits,fabricatedwithISSI'sadvanced

CMOS technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP package

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• Power supply:

NVP: V^DD2.5V (± 5%), VDDQ 2.5V (± 5%)

NLP: V^DD3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

• Industrial temperature available

• Lead-free available

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-250

2.6

-200

3.1

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany

publishedinformationandbeforeplacingordersforproducts.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00A

08/31/05

12 3 4 5 6 7...21

中文翻译

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与IS61NVP6436A相关器件

型号	品牌	获取价格	描述	数据表
IS61NVP6436A-200TQ	ISSI	获取价格	64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP6436A-200TQI	ISSI	获取价格	64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP6436A-250TQ	ISSI	获取价格	64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVP6436A-250TQI	ISSI	获取价格	64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVVF204836B	ISSI	获取价格	100 percent bus utilization
IS61NVVF409618B	ISSI	获取价格	100 percent bus utilization
IS61NVVP102436B-166B3LI	ISSI	获取价格	ZBT SRAM, 1MX36, 3.5ns, CMOS, PBGA165, 15 X 13 MM, 1 MM PITCH, LEAD FREE, PLASTIC, TFBGA-1
IS61NVVP204836B	ISSI	获取价格	100 percent bus utilization
IS61NVVP204836B-166TQLI	ISSI	获取价格	ZBT SRAM, 2MX36, 3.5ns, CMOS, PQFP100, TQFP-100
IS61NVVP25672	ISSI	获取价格	256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

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