Datasheet > IS61QDB21M18A

IS61QDB21M18A

更新时间： 2024-10-14 01:23:31

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
30页	772K
描述
512Kx36 and 1Mx18 configuration available

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IS61QDB21M18A 数据手册

IS61QDB21M18A

IS61QDB251236A

1Mx18, 512Kx36

18Mb QUAD (Burst 2) Synchronous SRAM

NOVEMBER 2014

DESCRIPTION

FEATURES

The

and

are



512Kx36 and 1Mx18 configuration available.

synchronous, high-performance CMOS static random access

memory (SRAM) devices. These SRAMs have separate I/Os,

eliminating the need for high-speed bus turnaround. The

rising edge of K clock initiates the read/write operation, and

all internal operations are self-timed. Refer to the

for a description of the

On-chip Delay-Locked Loop (DLL) for wide data

valid window.



Separate independent read and write ports with

concurrent read and write operations.

Synchronous pipeline read with EARLY write

operation.

basic operations of these

SRAMs.

Double Data Rate (DDR) interface for read and

write input ports.

The input address bus operates at double data rate. The

following are registered internally on the rising edge of the K

clock:



Fixed 2-bit burst for read and write operations.

Clock stop support.



Read address

Two input clocks (K and K#) for address and control

registering at rising edges only.

Read enable

Write enable



Two output clocks (C and C#) for data output control.

Byte writes

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.

Data-in for early writes



+1.8V core power supply and 1.5, 1.8V VDDQ, used

with 0.75, 0.9V VREF.

The following are registered on the rising edge of the K#

clock:



HSTL input and output levels.



Write address

Registered addresses, write and read controls, byte

writes, data in, and data outputs.

Byte writes

Data-in for second burst addresses



Full data coherency.

Boundary scan using limited set of JTAG 1149.1

functions.

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered half a cycle

earlier than the write address. The first data-in burst is

clocked at the same time as the write command signal, and

the second burst is timed to the following rising edge of the

K# clock.



Byte write capability.

Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array

Programmable impedance output drivers via 5x

user-supplied precision resistor.



During the burst read operation, the data-outs from the first

bursts are updated from output registers of the second rising

edge of the C# clock (starting 1.5 cycles later after read

command). The data-outs from the second bursts are

updated with the third rising edge of the C clock. The K and

K# clocks are used to time the data-outs whenever the C and

C# clocks are tied high.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

10/02/2014

12 3 4 5 6 7...30

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与IS61QDB21M18A相关器件

型号	品牌	获取价格	描述	数据表
IS61QDB21M18A-250B4LI	ISSI	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB21M36-250M3	ISSI	获取价格	36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB21M36-250M3L	ISSI	获取价格	36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB21M36A	ISSI	获取价格	1Mx36 and 2Mx18 configuration available
IS61QDB21M36A-250M3L	ISSI	获取价格	QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB21M36A-333B3	ISSI	获取价格	QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, TFBGA-165
IS61QDB22M18	ISSI	获取价格	36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M18-250M3	ISSI	获取价格	36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M18-250M3L	ISSI	获取价格	36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M18A	ISSI	获取价格	1Mx36 and 2Mx18 configuration available

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