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IS61QDB22M36-300M3I PDF预览

IS61QDB22M36-300M3I

更新时间： 2024-11-18 13:08:55
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器双倍数据速率时钟
页数 文件大小 规格书
27页 633K
描述
DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, LFBGA-165

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IS61QDB22M36-300M3I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：15 X 17 MM, 1 MM PITCH, LFBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.73
最长访问时间：0.45 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：300 MHzI/O 类型：SEPARATE
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：17 mm内存密度：75497472 bit
内存集成电路类型：DDR SRAM内存宽度：36
功能数量：1端子数量：165
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2MX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.5/1.8,1.8 V认证状态：Not Qualified
座面最大高度：1.4 mm最小待机电流：1.7 V
子类别：SRAMs最大压摆率：0.9 mA
最大供电电压 (Vsup)：1.89 V最小供电电压 (Vsup)：1.71 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：15 mm
Base Number Matches：1

IS61QDB22M36-300M3I 数据手册

 浏览型号IS61QDB22M36-300M3I的Datasheet PDF文件第2页浏览型号IS61QDB22M36-300M3I的Datasheet PDF文件第3页浏览型号IS61QDB22M36-300M3I的Datasheet PDF文件第4页浏览型号IS61QDB22M36-300M3I的Datasheet PDF文件第5页浏览型号IS61QDB22M36-300M3I的Datasheet PDF文件第6页浏览型号IS61QDB22M36-300M3I的Datasheet PDF文件第7页 
.
72 Mb (2M x 36 & 4M x 18)  
QUAD (Burst of 2) Synchronous SRAMs  
May 2009  
• Two echo clocks (CQ and CQ) that are delivered  
simultaneously with data.  
Features  
• 2M x 36 or 4M x 18.  
• +1.8V core power supply and 1.5, 1.8V VDDQ  
used with 0.75, 0.9V VREF  
,
• On-chip delay-locked loop (DLL) for wide data  
valid window.  
.
• HSTL input and output levels.  
• Separate read and write ports with concurrent  
read and write operations.  
• Registered addresses, write and read controls,  
byte writes, data in, and data outputs.  
• Synchronous pipeline read with early write oper-  
ation.  
• Full data coherency.  
• Boundary scan using limited set of JTAG 1149.1  
functions.  
• Double data rate (DDR) interface for read and  
write input ports.  
• Byte write capability.  
• Fixed 2-bit burst for read and write operations.  
• Clock stop support.  
• Fine ball grid array (FBGA) package  
- 15mm x 17mm body size  
- 1mm pitch  
• Two input clocks (K and K) for address and con-  
trol registering at rising edges only.  
- 165-ball (11 x 15) array  
• Two input clocks (C and C) for data output con-  
trol.  
• Programmable impedance output drivers via 5x  
user-supplied precision resistor.  
Description  
The 72Mb IS61QDB22M36 and  
• Write address  
IS61QDB24M18 are synchronous, high-perfor-  
mance CMOS static random access memory  
(SRAM) devices. These SRAMs have separate I/Os,  
eliminating the need for high-speed bus turnaround.  
The rising edge of K clock initiates the read/write  
operation, and all internal operations are self-timed.  
Refer to the Timing Reference Diagram for Truth  
Table on page 8 for a description of the basic opera-  
tions of these SRAMs.  
• Byte writes  
• Data-in for second burst addresses  
Byte writes can change with the corresponding data-  
in to enable or disable writes on a per-byte basis. An  
internal write buffer enables the data-ins to be regis-  
tered half a cycle earlier than the write address. The  
first data-in burst is clocked at the same time as the  
write command signal, and the second burst is timed  
to the following rising edge of the K clock.  
The input address bus operates at double data rate.  
The following are registered internally on the rising  
edge of the K clock:  
During the burst read operation, the data-outs from  
the first burst are updated from output registers off  
the second rising edge of the C clock (1.5 cycles  
later). The data-outs from the second burst are  
updated with the third rising edge of the C clock. The  
K and K clocks are used to time the data-outs when-  
ever the C and C clocks are tied high.  
• Read address  
• Read enable  
• Write enable  
• Byte writes  
• Data-in for early writes  
The device is operated with a single +1.8V power  
supply and is compatible with HSTL I/O interfaces.  
The following are registered on the rising edge of  
the K clock:  
Integrated Silicon Solution, Inc.  
1
Rev. A  
05/14/09  
1234567...27

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与IS61QDB22M36-300M3I相关器件

型号 品牌 获取价格 描述 数据表
IS61QDB22M36-300M3L ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M36A ISSI

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 		2Mx36 and 4Mx18 configuration available
IS61QDB22M36A-250M3L ISSI

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 		QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB22M36A-333B4LI ISSI

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 		QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB24M18-200M3L ISSI

获取价格

 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB24M18-250M3 ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB24M18-250M3L ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB24M18-250M3LI ISSI

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 		暂无描述
IS61QDB24M18-300M3 ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB24M18-300M3L ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs

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