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Datasheet > IS61QDB22M18A-333M3LI
IS61QDB22M18A-333M3LI PDF预览

IS61QDB22M18A-333M3LI

更新时间： 2024-11-21 20:04:23
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
29页 479K
描述
QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165

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IS61QDB22M18A-333M3LI 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：BGA包装说明：LBGA, BGA165,11X15,40
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.17最长访问时间：0.45 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：333 MHz
I/O 类型：SEPARATEJESD-30 代码：R-PBGA-B165
长度：17 mm内存密度：75497472 bit
内存集成电路类型：QDR SRAM内存宽度：36
功能数量：1端子数量：165
字数：2097152 words字数代码：2000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：2MX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：1.4 mm
最大待机电流：0.29 A最小待机电流：1.7 V
子类别：SRAMs最大压摆率：1.15 mA
最大供电电压 (Vsup)：1.89 V最小供电电压 (Vsup)：1.71 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM宽度：15 mm
Base Number Matches：1

IS61QDB22M18A-333M3LI 数据手册

 浏览型号IS61QDB22M18A-333M3LI的Datasheet PDF文件第2页浏览型号IS61QDB22M18A-333M3LI的Datasheet PDF文件第3页浏览型号IS61QDB22M18A-333M3LI的Datasheet PDF文件第4页浏览型号IS61QDB22M18A-333M3LI的Datasheet PDF文件第5页浏览型号IS61QDB22M18A-333M3LI的Datasheet PDF文件第6页浏览型号IS61QDB22M18A-333M3LI的Datasheet PDF文件第7页 
IS61QDB22M18A  
IS61QDB21M36A  
2Mx18, 1Mx36  
36Mb QUAD (Burst 2) Synchronous SRAM  
ADVANCED INFORMATION  
JULY 2012  
DESCRIPTION  
FEATURES  
The 36Mb IS61QDB21M36A and IS61QDB22M18A are  
1Mx36 and 2Mx18 configuration available.  
synchronous, high-performance CMOS static random access  
memory (SRAM) devices. These SRAMs have separate I/Os,  
eliminating the need for high-speed bus turnaround. The  
rising edge of K clock initiates the read/write operation, and  
all internal operations are self-timed. Refer to the Timing  
Reference Diagram for Truth Table for a description of the  
basic operations of these QUAD (Burst of 2) SRAMs.  
On-chip Delay-Locked Loop (DLL) for wide data  
valid window.  
Separate independent read and write ports with  
concurrent read and write operations.  
Synchronous pipeline read with EARLY write  
operation.  
Double Data Rate (DDR) interface for read and  
write input ports.  
The input address bus operates at double data rate. The  
following are registered internally on the rising edge of the K  
clock:  
Fixed 2-bit burst for read and write operations.  
Clock stop support.  
Read address  
Two input clocks (K and K#) for address and control  
registering at rising edges only.  
Read enable  
Write enable  
Two output clocks (C and C#) for data output control.  
Byte writes  
Two echo clocks (CQ and CQ#) that are delivered  
simultaneously with data.  
Data-in for early writes  
+1.8V core power supply and 1.5, 1.8V VDDQ, used  
with 0.75, 0.9V VREF.  
The following are registered on the rising edge of the K#  
clock:  
HSTL input and output interface.  
Write address  
Registered addresses, write and read controls, byte  
writes, data in, and data outputs.  
Byte writes  
Data-in for second burst addresses  
Full data coherency.  
Boundary scan using limited set of JTAG 1149.1  
functions.  
Byte writes can change with the corresponding data-in to  
enable or disable writes on a per-byte basis. An internal write  
buffer enables the data-ins to be registered half a cycle  
earlier than the write address. The first data-in burst is  
clocked at the same time as the write command signal, and  
the second burst is timed to the following rising edge of the  
K# clock.  
Byte write capability.  
Fine ball grid array (FBGA) package:  
13mmx15mm and 15mmx17mm body size  
165-ball (11 x 15) array  
Programmable impedance output drivers via 5x  
user-supplied precision resistor.  
During the burst read operation, the data-outs from the first  
bursts are updated from output registers of the second rising  
edge of the C# clock (starting 1.5 cycles later after read  
command). The data-outs from the second bursts are  
updated with the third rising edge of the C clock. The K and  
K# clocks are used to time the data-outs whenever the C and  
C# clocks are tied high.  
The device is operated with a single +1.8V power supply and  
is compatible with HSTL I/O interfaces.  
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
Rev. 00A  
1
7/05/2012  
1234567...29

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与IS61QDB22M18A-333M3LI相关器件

型号 品牌 获取价格 描述 数据表
IS61QDB22M18C-250M3L ISSI

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 		QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB22M36 ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M36-200M3L ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M36-250M3 ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M36-250M3L ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M36-300M3 ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M36-300M3I ISSI

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 		DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, LFBGA-165
IS61QDB22M36-300M3L ISSI

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 		72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M36A ISSI

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 		2Mx36 and 4Mx18 configuration available
IS61QDB22M36A-250M3L ISSI

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 		QDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165

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