Datasheet > 暂无类别数据> IS61QDB24M18-250M3LI

IS61QDB24M18-250M3LI

更新时间： 2024-11-21 13:08:55

品牌	Logo	应用领域
美国芯成 - ISSI		存储内存集成电路静态存储器双倍数据速率时钟
页数	文件大小	规格书
27页	633K
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72 Mb (2M x 36 & 4M x 18)

QUAD (Burst of 2) Synchronous SRAMs

May 2009

• Two echo clocks (CQ and CQ) that are delivered

simultaneously with data.

Features

• 2M x 36 or 4M x 18.

• +1.8V core power supply and 1.5, 1.8V V_DDQ

used with 0.75, 0.9V V_REF

• On-chip delay-locked loop (DLL) for wide data

valid window.

• HSTL input and output levels.

• Separate read and write ports with concurrent

read and write operations.

• Registered addresses, write and read controls,

byte writes, data in, and data outputs.

• Synchronous pipeline read with early write oper-

ation.

• Full data coherency.

• Boundary scan using limited set of JTAG 1149.1

functions.

• Double data rate (DDR) interface for read and

write input ports.

• Byte write capability.

• Fixed 2-bit burst for read and write operations.

• Clock stop support.

• Fine ball grid array (FBGA) package

- 15mm x 17mm body size

- 1mm pitch

• Two input clocks (K and K) for address and con-

trol registering at rising edges only.

- 165-ball (11 x 15) array

• Two input clocks (C and C) for data output con-

trol.

• Programmable impedance output drivers via 5x

user-supplied precision resistor.

Description

The 72Mb IS61QDB22M36 and

• Write address

IS61QDB24M18 are synchronous, high-perfor-

mance CMOS static random access memory

(SRAM) devices. These SRAMs have separate I/Os,

eliminating the need for high-speed bus turnaround.

The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed.

Refer to the Timing Reference Diagram for Truth

Table on page 8 for a description of the basic opera-

tions of these SRAMs.

• Byte writes

• Data-in for second burst addresses

Byte writes can change with the corresponding data-

in to enable or disable writes on a per-byte basis. An

internal write buffer enables the data-ins to be regis-

tered half a cycle earlier than the write address. The

first data-in burst is clocked at the same time as the

write command signal, and the second burst is timed

to the following rising edge of the K clock.

The input address bus operates at double data rate.

The following are registered internally on the rising

edge of the K clock:

During the burst read operation, the data-outs from

the first burst are updated from output registers off

the second rising edge of the C clock (1.5 cycles

later). The data-outs from the second burst are

updated with the third rising edge of the C clock. The

K and K clocks are used to time the data-outs when-

ever the C and C clocks are tied high.

• Read address

• Read enable

• Write enable

• Byte writes

• Data-in for early writes

The device is operated with a single +1.8V power

supply and is compatible with HSTL I/O interfaces.

The following are registered on the rising edge of

the K clock:

Integrated Silicon Solution, Inc.

Rev. A

05/14/09

12 3 4 5 6 7...27

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与IS61QDB24M18-250M3LI相关器件

型号	品牌	获取价格	描述	数据表
IS61QDB24M18-300M3	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB24M18-300M3L	ISSI	获取价格	72 Mb (2M x 36 & 4M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB24M18A	ISSI	获取价格	2Mx36 and 4Mx18 configuration available
IS61QDB24M18A-250B4LI	ISSI	获取价格	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB24M18A-300B4LI	ISSI	获取价格	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB24M18A-300M3L	ISSI	获取价格	QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB251236A	ISSI	获取价格	512Kx36 and 1Mx18 configuration available
IS61QDB251236A-250M3L	ISSI	获取价格	IC SRAM 18M PARALLEL 165LFBGA
IS61QDB251236A-300M3L	ISSI	获取价格	QDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB41M18A	ISSI	获取价格	512Kx36 and 1Mx18 configuration available

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