Datasheet > IS61QDB41M36C-333M3LI

IS61QDB41M36C-333M3LI

更新时间： 2024-10-13 20:11:11

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器内存集成电路
页数	文件大小	规格书
32页	804K
描述
QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165

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IS61QDB41M36C-333M3LI 技术参数

生命周期：	Active	包装说明：	LBGA,
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.67
最长访问时间：	0.45 ns	JESD-30 代码：	R-PBGA-B165
长度：	17 mm	内存密度：	37748736 bit
内存集成电路类型：	QDR SRAM	内存宽度：	36
功能数量：	1	端子数量：	165
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	1MX36
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	座面最大高度：	1.4 mm
最大供电电压 (Vsup)：	1.89 V	最小供电电压 (Vsup)：	1.71 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	15 mm
Base Number Matches：	1

IS61QDB41M36C-333M3LI 数据手册

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IS61QDB42M18C

IS61QDB41M36C

2Mx18, 1Mx36

36Mb QUAD (Burst 4) SYNCHRONOUS SRAM

APRIL 2016

FEATURES

DESCRIPTION

The 36Mb IS61QDB41M36C and IS61QDB42M18C are

synchronous, high-performance CMOS static random access

memory (SRAM) devices. These SRAMs have separate I/Os,

eliminating the need for high-speed bus turnaround. The

rising edge of K clock initiates the read/write operation, and

all internal operations are self-timed. Refer to the Timing

Reference Diagram for Truth Table for a description of the

basic operations of these QUAD (Burst of 4) SRAMs.



1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data

valid window.



Separate independent read and write ports with

concurrent read and write operations.



Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interface for read and

write input ports.

Read and write addresses are registered on alternating rising

edges of the K clock. Reads and writes are performed in

double data rate. The following are registered internally on

the rising edge of the K clock:



1.5 cycle read latency.

Fixed 4-bit burst for read and write operations.

Clock stop support.



Read/write address

Two input clocks (K and K#) for address and control

registering at rising edges only.

Read enable



Two output clocks (C and C#) for data output control.

Write enable

Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.

Byte writes for burst addresses 1 and 3

Data-in for burst addresses 1 and 3



+1.8V core power supply and 1.5, 1.8V VDDQ, used

with 0.75, 0.9V VREF.

The following are registered on the rising edge of the K#

clock:



HSTL input and output levels.



Byte writes for burst addresses 2 and 4

Registered addresses, write and read controls, byte

writes, data in, and data outputs.



Data-in for burst addresses 2 and 4



Full data coherency.

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after

the write address. The first data-in burst is clocked one cycle

later than the write command signal, and the second burst is

timed to the following rising edge of the K# clock. Two full

clock cycles are required to complete a write operation.

Boundary scan using limited set of JTAG 1149.1

functions.



Byte write capability.

Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array



Programmable impedance output drivers via 5x

user-supplied precision resistor.

During the burst read operation, the data-outs from the first

and third bursts are updated from output registers of the

second and third rising edges of the C# clock (starting 1.5

cycles later after read command). The data-outs from the

second and fourth bursts are updated with the third and

fourth rising edges of the C clock. The K and K# clocks are

used to time the data-outs whenever the C and C# clocks are

tied high. Two full clock cycles are required to complete a

read operation.

The device is operated with a single +1.8V power supply and

is compatible with HSTL I/O interfaces.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A1

04/06/2016

12 3 4 5 6 7...32

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与IS61QDB41M36C-333M3LI相关器件

型号	品牌	获取价格	描述	数据表
IS61QDB41M36C-400M3I	ISSI	获取价格	QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LFBGA-165
IS61QDB42M18-200M3	ISSI	获取价格	36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs
IS61QDB42M18A	ISSI	获取价格	Synchronous pipeline read with late write operation
IS61QDB42M18A-333M3LI	ISSI	获取价格	QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB42M18C-250M3	ISSI	获取价格	IC SRAM 36M PARALLEL 165LFBGA
IS61QDB42M18C-250M3L	ISSI	获取价格	IC SRAM 36M PARALLEL 165LFBGA
IS61QDB42M18C-300M3L	ISSI	获取价格	QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB42M18C-333M3I	ISSI	获取价格	IC SRAM 36M PARALLEL 165LFBGA
IS61QDB42M18C-333M3L	ISSI	获取价格	QDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB42M18C-333M3LI	ISSI	获取价格	IC SRAM 36M PARALLEL 165LFBGA

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