Datasheet > 存储 > SRAM> IS61NVVP25672-200B

IS61NVVP25672-200B

更新时间： 2024-11-18 03:18:43

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
29页	161K
描述
256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

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IS61NVVP25672

IS61NVVP51236

ISSI

ADVANCE INFORMATION

JULY 2002

256K x 72 and 512K x 36, 18Mb

PIPELINE 'NO WAIT' STATE BUS SRAM

FEATURES

DESCRIPTION

The 16 Meg 'NVVP' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

network and communications customers. They are

organized as 256K words by 72 bits, 512K words

by 36 bits and are fabricated with ISSI's advanced CMOS

technology.

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

• Interleaved or linear burst sequence control

using MODE input

• Power Down mode

Allsynchronousinputspassthroughregistersarecontrolled

byapositive-edge-triggeredsingleclockinput.Operations

may be suspended and all synchronous inputs ignored

when Clock Enable, CKE is HIGH. In this state the internal

device will hold their previous values.

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 119-ball PBGA (x36) and

209-ball (x72) PBGA packages

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

• Single +1.8V (± 5%) power supply

• JTAG Boundary Scan

• Industrial temperature available

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when WE is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence.WhentiedHIGH,theinterleavedburstsequence

is selected. When tied LOW, the linear burst sequence is

selected.

FAST ACCESS TIME

Symbol

tKQ

Parameter

-250

2.6

-200

3.2

Units

Clock Access Time

Cycle Time

tKC

Frequency

250

200

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

ADVANCEDINFORMATION Rev. 00A

07/17/02

12 3 4 5 6 7...29

中文翻译

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与IS61NVVP25672-200B相关器件

型号	品牌	获取价格	描述	数据表
IS61NVVP25672-200BI	ISSI	获取价格	256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVVP25672-250B	ISSI	获取价格	256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVVP25672-250BI	ISSI	获取价格	256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVVP409618B	ISSI	获取价格	100 percent bus utilization
IS61NVVP51236	ISSI	获取价格	256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVVP51236-200B	ISSI	获取价格	256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVVP51236-200BI	ISSI	获取价格	256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVVP51236-250B	ISSI	获取价格	256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
IS61NVVP51236-250BI	ISSI	获取价格	256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
IS61NW6432	ICSI	获取价格	64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE

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