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IS61NVVP51236-200B PDF预览

IS61NVVP51236-200B

更新时间： 2024-11-18 03:18:43
品牌 Logo 应用领域
美国芯成 - ISSI 存储内存集成电路静态存储器
页数 文件大小 规格书
29页 161K
描述
256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

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中文翻译

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IS61NVVP51236-200B 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：PLASTIC, BGA-119针数：119
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
Is Samacsys：N最长访问时间：3 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：18874368 bit内存集成电路类型：ZBT SRAM
内存宽度：36功能数量：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512KX36封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：240认证状态：Not Qualified
座面最大高度：2.41 mm最大供电电压 (Vsup)：1.89 V
最小供电电压 (Vsup)：1.71 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IS61NVVP51236-200B 数据手册

 浏览型号IS61NVVP51236-200B的Datasheet PDF文件第2页浏览型号IS61NVVP51236-200B的Datasheet PDF文件第3页浏览型号IS61NVVP51236-200B的Datasheet PDF文件第4页浏览型号IS61NVVP51236-200B的Datasheet PDF文件第5页浏览型号IS61NVVP51236-200B的Datasheet PDF文件第6页浏览型号IS61NVVP51236-200B的Datasheet PDF文件第7页 
®
IS61NVVP25672  
IS61NVVP51236  
ISSI  
ADVANCE INFORMATION  
JULY 2002  
256K x 72 and 512K x 36, 18Mb  
PIPELINE 'NO WAIT' STATE BUS SRAM  
FEATURES  
DESCRIPTION  
The 16 Meg 'NVVP' product family feature high-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, 'no wait' state, device for  
network and communications customers. They are  
organized as 256K words by 72 bits, 512K words  
by 36 bits and are fabricated with ISSI's advanced CMOS  
technology.  
• 100 percent bus utilization  
• No wait cycles between Read and Write  
• Internal self-timed write cycle  
• Individual Byte Write Control  
• Single R/W (Read/Write) control pin  
• Clock controlled, registered address,  
data and control  
Incorporating a 'no wait' state feature, wait cycles are  
eliminated when the bus switches from read to write, or  
write to read. This device integrates a 2-bit burst counter,  
high-speed SRAM core, and high-drive capability outputs  
into a single monolithic circuit.  
• Interleaved or linear burst sequence control  
using MODE input  
• Power Down mode  
Allsynchronousinputspassthroughregistersarecontrolled  
byapositive-edge-triggeredsingleclockinput.Operations  
may be suspended and all synchronous inputs ignored  
when Clock Enable, CKE is HIGH. In this state the internal  
device will hold their previous values.  
• Common data inputs and data outputs  
• CKE pin to enable clock and suspend operation  
• JEDEC 119-ball PBGA (x36) and  
209-ball (x72) PBGA packages  
All Read, Write and Deselect cycles are initiated by the  
ADV input. When the ADV is HIGH the internal burst  
counter is incremented. New external addresses can be  
loaded when ADV is LOW.  
• Single +1.8V (± 5%) power supply  
• JTAG Boundary Scan  
• Industrial temperature available  
Write cycles are internally self-timed and are initiated by  
the rising edge of the clock inputs and when WE is LOW.  
Separate byte enables allow individual bytes to be written.  
A burst mode pin (MODE) defines the order of the burst  
sequence.WhentiedHIGH,theinterleavedburstsequence  
is selected. When tied LOW, the linear burst sequence is  
selected.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-250  
2.6  
4
-200  
3.2  
5
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
ns  
Frequency  
250  
200  
MHz  
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
ADVANCEDINFORMATION Rev. 00A  
1
07/17/02  
1234567...29

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