Datasheet > IS61NW6432

IS61NW6432

更新时间： 2024-10-13 02:54:51

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
14页	878K
描述
64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE

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IS61NW6432 数据手册

IS61NW6432

64K x 32 SYNCHRONOUS STATIC RAM

WITH NO-WAIT STATE BUS FEATURE

FEATURES

Fast access time:

DESCRIPTION

The IS61NW6432 is a high-speed, low-power synchronous

static RAM designed to provide a burstable, high-performance,

no-wait bus, secondary cache for the Pentium, 680X0, and

Power PC microprocessors. It is organized as 65,536 words

by 32 bits, fabricated with ICSI's advanced CMOS technology.

5 ns-100 MHz; 6 ns-83 MHz;

7 ns-75 MHz; 8ns-66 MHz;

No wait cycles between Read and write

Internal self-timed write cycle

Individual byte write Control

Incorporating a no-wait bus, wait cycles are eliminated when

the bus switches from read to write, or write to read. This

device integrates a 2-bit burst counter, high-speed SRAM

core, and high-drive capability outputs into a single monolithic

circuit.

Clock controlled, registered address, data and

control

Pentium^TMor Inear burst sequence control using

MODE input

Three chip enables for simple depth depth

expansion and adress pipelining

All synchronous inputs pass through registers controlled by a

Positive-edge-trggered clock input. Operations may be sus-

pended and all synchronous inputs ignored when Clock Enable,

CEN is HIGH. In this state the internal device will hold their

previous values.

Common data inputs and data outputs

JEDEC 100-pin LQFP and PQFP package

Single+3.3V power supply

Optional data strobe pin (#80) for latching data

(See page 12 for detailed timing)

When the ADV/LD is HIGH the internal burst counter is

incremented. New external addresses can be loaded when

ADV/LD is LOW.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock inputs and when RD/WE is LOW.

Separate byte enables allow indiviual bytes to be written. BW1

controls I/O1-I/P8; BW2 controls I/O9-I/O16;BW3 controls I/

O17-I/O24; BW4 controls I/O25-I/O32. All Bytes are written

when BW1, BW2, BW3, and BW4 are LOW.

MODE pin upon power up is in interleave burst mode. It can be

connected to GND or Vcc^Qto alter power up state.

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

Integrated Circuit Solution Inc.

SSR006-0B

12 3 4 5 6 7...14

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与IS61NW6432相关器件

型号	品牌	获取价格	描述	数据表
IS61NW6432-5PQ	ICSI	获取价格	64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
IS61NW6432-5TQ	ICSI	获取价格	64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
IS61NW6432-6PQ	ICSI	获取价格	64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
IS61NW6432-6TQ	ICSI	获取价格	64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
IS61NW6432-7PQ	ICSI	获取价格	64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
IS61NW6432-7TQ	ICSI	获取价格	64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
IS61NW6432-8PQ	ICSI	获取价格	64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
IS61NW6432-8TQ	ICSI	获取价格	64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
IS61QDB21M18A	ISSI	获取价格	512Kx36 and 1Mx18 configuration available
IS61QDB21M18A-250B4LI	ISSI	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165

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