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IS61NW6432-5TQ PDF预览

IS61NW6432-5TQ

更新时间： 2024-10-13 02:54:51
品牌 Logo 应用领域
矽成 - ICSI 存储内存集成电路静态存储器
页数 文件大小 规格书
14页 878K
描述
64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE

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中文翻译

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IS61NW6432-5TQ 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：QFP, QFP100,.63X.87Reach Compliance Code：unknown
风险等级：5.87Is Samacsys：N
最长访问时间：5 nsI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
内存密度：2097152 bit内存集成电路类型：ZBT SRAM
内存宽度：32端子数量：100
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL电源：3.3 V
认证状态：Not Qualified最大待机电流：0.06 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.23 mA标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUADBase Number Matches：1

IS61NW6432-5TQ 数据手册

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IS61NW6432  
64K x 32 SYNCHRONOUS STATIC RAM  
WITH NO-WAIT STATE BUS FEATURE  
FEATURES  
• Fast access time:  
DESCRIPTION  
The IS61NW6432 is a high-speed, low-power synchronous  
static RAM designed to provide a burstable, high-performance,  
no-wait bus, secondary cache for the Pentium, 680X0, and  
Power PC microprocessors. It is organized as 65,536 words  
by 32 bits, fabricated with ICSI's advanced CMOS technology.  
— 5 ns-100 MHz; 6 ns-83 MHz;  
— 7 ns-75 MHz; 8ns-66 MHz;  
• No wait cycles between Read and write  
• Internal self-timed write cycle  
• Individual byte write Control  
Incorporating a no-wait bus, wait cycles are eliminated when  
the bus switches from read to write, or write to read. This  
device integrates a 2-bit burst counter, high-speed SRAM  
core, and high-drive capability outputs into a single monolithic  
circuit.  
• Clock controlled, registered address, data and  
control  
• PentiumTM or Inear burst sequence control using  
MODE input  
• Three chip enables for simple depth depth  
expansion and adress pipelining  
All synchronous inputs pass through registers controlled by a  
Positive-edge-trggered clock input. Operations may be sus-  
pended and all synchronous inputs ignored when Clock Enable,  
CEN is HIGH. In this state the internal device will hold their  
previous values.  
• Common data inputs and data outputs  
• JEDEC 100-pin LQFP and PQFP package  
• Single+3.3V power supply  
• Optional data strobe pin (#80) for latching data  
(See page 12 for detailed timing)  
When the ADV/LD is HIGH the internal burst counter is  
incremented. New external addresses can be loaded when  
ADV/LD is LOW.  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock inputs and when RD/WE is LOW.  
Separate byte enables allow indiviual bytes to be written. BW1  
controls I/O1-I/P8; BW2 controls I/O9-I/O16;BW3 controls I/  
O17-I/O24; BW4 controls I/O25-I/O32. All Bytes are written  
when BW1, BW2, BW3, and BW4 are LOW.  
MODE pin upon power up is in interleave burst mode. It can be  
connected to GND or VccQ to alter power up state.  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
SSR006-0B  
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