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IS61NW6432-8TQ PDF预览

IS61NW6432-8TQ

更新时间： 2024-11-18 02:54:51
品牌 Logo 应用领域
矽成 - ICSI 内存集成电路静态存储器
页数 文件大小 规格书
14页 878K
描述
64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE

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中文翻译

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IS61NW6432-8TQ 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：QFP, QFP100,.63X.87Reach Compliance Code：unknown
风险等级：5.88最长访问时间：8 ns
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0内存密度：2097152 bit
内存集成电路类型：ZBT SRAM内存宽度：32
端子数量：100字数：65536 words
字数代码：64000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：64KX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK并行/串行：PARALLEL
电源：3.3 V认证状态：Not Qualified
最大待机电流：0.06 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.2 mA
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.635 mm端子位置：QUAD
Base Number Matches：1

IS61NW6432-8TQ 数据手册

 浏览型号IS61NW6432-8TQ的Datasheet PDF文件第2页浏览型号IS61NW6432-8TQ的Datasheet PDF文件第3页浏览型号IS61NW6432-8TQ的Datasheet PDF文件第4页浏览型号IS61NW6432-8TQ的Datasheet PDF文件第5页浏览型号IS61NW6432-8TQ的Datasheet PDF文件第6页浏览型号IS61NW6432-8TQ的Datasheet PDF文件第7页 
IS61NW6432  
64K x 32 SYNCHRONOUS STATIC RAM  
WITH NO-WAIT STATE BUS FEATURE  
FEATURES  
• Fast access time:  
DESCRIPTION  
The IS61NW6432 is a high-speed, low-power synchronous  
static RAM designed to provide a burstable, high-performance,  
no-wait bus, secondary cache for the Pentium, 680X0, and  
Power PC microprocessors. It is organized as 65,536 words  
by 32 bits, fabricated with ICSI's advanced CMOS technology.  
— 5 ns-100 MHz; 6 ns-83 MHz;  
— 7 ns-75 MHz; 8ns-66 MHz;  
• No wait cycles between Read and write  
• Internal self-timed write cycle  
• Individual byte write Control  
Incorporating a no-wait bus, wait cycles are eliminated when  
the bus switches from read to write, or write to read. This  
device integrates a 2-bit burst counter, high-speed SRAM  
core, and high-drive capability outputs into a single monolithic  
circuit.  
• Clock controlled, registered address, data and  
control  
• PentiumTM or Inear burst sequence control using  
MODE input  
• Three chip enables for simple depth depth  
expansion and adress pipelining  
All synchronous inputs pass through registers controlled by a  
Positive-edge-trggered clock input. Operations may be sus-  
pended and all synchronous inputs ignored when Clock Enable,  
CEN is HIGH. In this state the internal device will hold their  
previous values.  
• Common data inputs and data outputs  
• JEDEC 100-pin LQFP and PQFP package  
• Single+3.3V power supply  
• Optional data strobe pin (#80) for latching data  
(See page 12 for detailed timing)  
When the ADV/LD is HIGH the internal burst counter is  
incremented. New external addresses can be loaded when  
ADV/LD is LOW.  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock inputs and when RD/WE is LOW.  
Separate byte enables allow indiviual bytes to be written. BW1  
controls I/O1-I/P8; BW2 controls I/O9-I/O16;BW3 controls I/  
O17-I/O24; BW4 controls I/O25-I/O32. All Bytes are written  
when BW1, BW2, BW3, and BW4 are LOW.  
MODE pin upon power up is in interleave burst mode. It can be  
connected to GND or VccQ to alter power up state.  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
SSR006-0B  
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与IS61NW6432-8TQ相关器件

型号 品牌 获取价格 描述 数据表
IS61QDB21M18A ISSI

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 		512Kx36 and 1Mx18 configuration available
IS61QDB21M18A-250B4LI ISSI

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 		QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB21M36-250M3 ISSI

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 		36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB21M36-250M3L ISSI

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 		36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB21M36A ISSI

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 		1Mx36 and 2Mx18 configuration available
IS61QDB21M36A-250M3L ISSI

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 		QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, LFBGA-165
IS61QDB21M36A-333B3 ISSI

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 		QDR SRAM, 1MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, TFBGA-165
IS61QDB22M18 ISSI

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 		36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M18-250M3 ISSI

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 		36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M18-250M3L ISSI

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 		36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs

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