®
IS61NVVP25672
IS61NVVP51236
ISSI
ADVANCE INFORMATION
JULY 2002
256K x 72 and 512K x 36, 18Mb
PIPELINE 'NO WAIT' STATE BUS SRAM
FEATURES
DESCRIPTION
The 16 Meg 'NVVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 256K words by 72 bits, 512K words
by 36 bits and are fabricated with ISSI's advanced CMOS
technology.
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
• Interleaved or linear burst sequence control
using MODE input
• Power Down mode
Allsynchronousinputspassthroughregistersarecontrolled
byapositive-edge-triggeredsingleclockinput.Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 119-ball PBGA (x36) and
209-ball (x72) PBGA packages
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
• Single +1.8V (± 5%) power supply
• JTAG Boundary Scan
• Industrial temperature available
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence.WhentiedHIGH,theinterleavedburstsequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
tKQ
Parameter
-250
2.6
4
-200
3.2
5
Units
ns
Clock Access Time
Cycle Time
tKC
ns
Frequency
250
200
MHz
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCEDINFORMATION Rev. 00A
1
07/17/02