Datasheet > IDT79RC32332

IDT79RC32332

更新时间： 2024-09-14 22:26:15

品牌	Logo	应用领域
艾迪悌 - IDT		通信
页数	文件大小	规格书
47页	991K
描述
IDT Interprise Integrated Communications Processor

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IDT79RC32332 数据手册

IDT^TMInterprise^TMIntegrated

Communications Processor

79RC32355

◆

SDRAM Controller

2 memory banks, non-interleaved, 512 MB total

Features List

–

◆

RC32300 32-bit Microprocessor

32-bit wide data path

Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips

SODIMM support

Stays on page between transfers

Automatic refresh generation

–

Enhanced MIPS-II ISA

Enhanced MIPS-IV cache prefetch instruction

DSP Instructions

MMU with 16-entry TLB

8KB Instruction Cache, 2-way set associative

2KB Data Cache, 2-way set associative

Per line cache locking

Write-through and write-back cache management

Debug interface through the EJTAG port

Big or Little endian support

◆

Peripheral Device Controller

–

26-bit address bus

32-bit data bus with variable width support of 8-,16-, or 32-bits

8-bit boot ROM support

6 banks available, up to 64MB per bank

Supports Flash ROM, PROM, SRAM, dual-port memory, and

peripheral devices

–

◆

Interrupt Controller

Allows status of each interrupt to be read and masked

–

I C

–

Supports external wait-state generation, Intel or Motorola style

Write protect capability

Direct control of optional external data transceivers

Flexible I C standard serial interface to connect to a variety of

peripherals

◆

System Integrity

–

Standard and fast mode timing support

Configurable 7 or 10-bit addressable slave

–

Programmable system watchdog timer resets system on time-

out

◆

UARTs

–

Programmable bus transaction times memory and peripheral

transactions and generates a warm reset on time-out

–

Two 16550 Compatible UARTs

Baud rate support up to 1.5 Mb/s

◆

DMA

◆

Counter/Timers

–

General Purpose I/O Pins (GPIOP)

–

16 DMA channels

Three general purpose 32-bit counter/timers

Services on-chip and external peripherals

Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O

transfers

–

36 individually programmable pins

Each pin programmable as input, output, or alternate function

Input can be an interrupt or NMI source

–

Supports flexible descriptor based operation and chaining via

linked lists of records (scatter / gather capability)

Supports unaligned transfers

Input can also be active high or active low

–

Supports burst transfers

Block Diagram

RC32300

CPU Core

Interrupt

Controller

10/100

USB

Interface

ICE

EJTAG

Ethernet

Interface

MMU

Watchdog

Timer

3 Counter

Timers

16 Channel

DMA

I. Cache

D. Cache

Controller

Arbiter

SDRAM &

Device

Controller

TDM

Interface

GPIO

Interface

ATM

Interface

2 UARTS

(16550)

I C

Ext. Bus

Master

Controller

Utopia 1 / 2

TDM Bus

GPIO Pins

I C Bus

Memory &

Peripheral Bus

Ch. 2

Ch. 1

Serial Channels

Figure 1 RC32355 Internal Block Diagram

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 47

May 25, 2004

DSC 5900

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与IDT79RC32332相关器件

型号	品牌	获取价格	描述	数据表
IDT79RC32332-100DHI	IDT	获取价格	Microprocessor
IDT79RC32332-133DH	IDT	获取价格	Microprocessor
IDT79RC32332-133DHI	IDT	获取价格	Microprocessor
IDT79RC32334-100BBI	IDT	获取价格	Microprocessor
IDT79RC32334-133BB	IDT	获取价格	Microprocessor
IDT79RC32355	IDT	获取价格	IDT Interprise Integrated Communications Processor
IDT79RC32438	IDT	获取价格	IDTTM InterpriseTM Integrated Communications Processor
IDT79RC32H435-266BC	IDT	获取价格	RISC Microprocessor, 32-Bit, 266MHz, PBGA256
IDT79RC32H435-350BC	IDT	获取价格	RISC Microprocessor, 32-Bit, 350MHz, PBGA256
IDT79RC32H435-350BCI	IDT	获取价格	RISC Microprocessor, 32-Bit, 350MHz, PBGA256

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