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IDT79RC32T332-100DH PDF预览

IDT79RC32T332-100DH

更新时间: 2024-11-29 07:15:19
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
30页 431K
描述
Microprocessor, 32-Bit, 100MHz, CMOS, PQFP208

IDT79RC32T332-100DH 数据手册

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IDTTM InterpriseTM Integrated  
Communications Processor  
3.3V and 2.5V Devices  
79RC32332  
Cache locking per line  
Device Overview  
Programmable on a page basis to implement a write-through  
no write allocate, write-through write allocate, or write-back  
algorithms for cache management  
The RC32332 device is a member of the IDT™ Interprise™ family of  
integrated communications processors. This product incorporates a  
high-performance, low-cost 32-bit CPU core with functionality common  
to a large number of embedded applications. The RC32332 integrates  
these functions to enable the use of low-cost PC commodity market  
memory and I/O devices, allowing the aggressive price/performance  
characteristics of the CPU to be realized quickly into low-cost systems.  
Compatible with a wide variety of operating systems  
Local Bus Interface  
Interrupt Controller simplifies exception management  
Four general purpose 32-bit timer/counters  
Programmable I/O (PIO)  
Up to 75 MHz operation  
23-bit address bus  
32-bit data bus  
Direct control of local memory and peripherals  
Programmable system watch-dog timers  
Big or little endian support  
The RC32332 device is available with either a 3.3V or 2.5V operating  
voltage. Differences between the two versions are noted where appli-  
cable.  
Features  
RC32300 32-bit Microprocessor  
Input/Output/Interrupt source  
Individually programmable  
Up to 150 MHz operation  
Enhanced MIPS-II Instruction Set Architecture (ISA)  
Cache prefetch instruction  
Conditional move instruction  
DSP instructions  
Supports big or little endian operation  
MMU with 32 page TLB  
8KB Instruction Cache, 2-way set associative  
2KB Data Cache, 2-way set associative  
SDRAM Controller (32-bit memory only)  
4 banks, non-interleaved  
Up to 512MB total SDRAM memory supported  
Implements full, direct control of discrete, SODIMM, or DIMM  
memories  
Supports 16Mb through 512Mb SDRAM device depths  
Automatic refresh generation  
Block Diagram  
Interrupt Contro  
l
EJTAG  
In-Circuit Emulator Interface  
Programmable I/O  
SPI Control  
32-bit Timers  
RISCore 32300  
Enhanced MIPS-II ISA Compatible  
Integer CPU  
RC5000  
CP0  
DMA Control  
UART  
Local  
Memory/IO  
Control  
32-page  
TLB  
IPBus  
Bridge  
SDRAM  
Control  
IDT  
Peripheral  
Bus  
8KB  
2-set  
2KB  
2-set, Lockable  
Lockable  
Instr. Cache  
Data Cache  
PCI Bridge  
Figure 1 RC32332 Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 30  
May 4, 2004  
DSC 5701  
© 2004 Integrated Device Technology, Inc.  

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