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IDT79RC32T336-180BCI PDF预览

IDT79RC32T336-180BCI

更新时间： 2024-11-06 14:51:31
品牌 Logo 应用领域
艾迪悌 - IDT 外围集成电路
页数 文件大小 规格书
44页 769K
描述
RISC Microprocessor, 32-Bit, 180MHz, CMOS, PBGA256

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IDT79RC32T336-180BCI 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：not_compliant风险等级：5.92
Is Samacsys：N位大小：32
JESD-30 代码：S-PBGA-B256JESD-609代码：e0
湿度敏感等级：3端子数量：256
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA256,16X16,40封装形状：SQUARE
封装形式：GRID ARRAY电源：2.5,3.3 V
认证状态：Not Qualified速度：180 MHz
子类别：Microprocessors表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
uPs/uCs/外围集成电路类型：MICROPROCESSOR, RISCBase Number Matches：1

IDT79RC32T336-180BCI 数据手册

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IDTTM InterpriseTM Integrated  
Communications Processor  
RC32336  
–
–
MMU  
Device Overview  
–
–
16-entry TLB  
The RC32336 device is a member of the IDT™ Interprise™ family of  
integrated communications processors. It provides an effective solution  
for small office/home office (SOHO) applications including gateways and  
both single-band and dual-band wireless access points. Featuring a  
MIPS compatible CPU core, the device also includes a memory  
controller supporting SDRAM memory, a PCI interface featuring an on-  
chip arbiter to support up to three external devices, a PCMCIA interface  
that supports a single I/O device, and two integrated on-chip 10/100  
Ethernet MACs to enable WAN and LAN connectivity.  
Supports variable page sizes and enhanced write algo-  
rithm  
–
Supports variable number of locked entries  
8KB Instruction Cache  
–
–
–
–
–
–
2-way set associative  
LRU replacement algorithm  
4 word line size  
Sub-block ordering  
Word parity  
Per line cache locking  
The key features of the RC32336 enable SOHO applications at  
unmatched price/performance points. The MIPS-compatible CPU core  
has the required bandwidth to enable a WAP application with the latest  
wireless security protocols, WPA and 802.11i, which include the enter-  
prise-level user authentication schemes 802.1x and Extensible Authenti-  
cation Protocol (EAP). The ability to connect and support the bandwidth  
requirements of one or two WLAN modules is made possible by the high  
bandwidth PCI and PCMCIA interfaces. Also, the device has been archi-  
tected to provide high speed LAN to WAN routing bandwidth through the  
Ethernet MACs while simultaneously driving data through the other on-  
chip interfaces.  
–
2KB Data Cache  
–
–
–
–
–
–
–
2-way set associative  
LRU replacement algorithm  
4 word line size  
Sub-block ordering  
Byte parity  
Per line cache locking  
Can be programmed on a page basis to implement write-  
through no write allocate, write-through write allocate, or  
write-back algorithms  
–
Enhanced EJTAG and JTAG Interfaces  
–
Compatible with IEEE Std. 1149.1-1990  
Features List  
◆
RC32300 32-bit CPU core  
–
–
32-bit MIPS instruction set  
Supports big or little endian operation  
Block Diagram  
MII  
MII  
SPI Bus  
MIPS-32  
CPU Core  
Interrupt  
Controller  
.
.
2 Ethernet  
EJTAG  
10/100  
Interfaces  
MMU  
I. Cache  
Bus/System  
Integrity  
Monitor  
SPI  
Controller  
D. Cache  
DMA  
Controller  
Arbiter  
TM  
IPBus  
SDRAM &  
PCI  
Master/Target  
Interface  
Device  
GPIO  
Interface  
UART  
(16550)  
Controllers  
3 Counter  
Timers  
PCI Arbiter  
(Host Mode)  
PCI Bus  
Memory &  
Peripheral Bus  
(including PCMCIA)  
GPIO Pins  
Serial Channel  
Figure 1 RC32336 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 44  
May 25, 2004  
DSC 6405  
© 2003 Integrated Device Technology, Inc.  
1234567...44

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