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IDT79RC32V332-133DPI PDF预览

IDT79RC32V332-133DPI

更新时间: 2024-11-05 23:58:27
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页数 文件大小 规格书
26页 398K
描述
MICROPROCESSOR|32-BIT|QFP|208PIN|PLASTIC

IDT79RC32V332-133DPI 数据手册

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RISCoreTM 32300 Family  
Integrated Processor  
79RC32332  
Programmable I/O (PIO)  
Input/Output/Interrupt source  
Individually programmable  
RC32300 32-bit Microprocessor  
Up to 133 MHz operation  
Enhanced MIPS-II Instruction Set Architecture (ISA)  
Cache prefetch instruction  
Conditional move instruction  
DSP instructions  
Supports big or little endian operation  
MMU with 32 page TLB  
8kB Instruction Cache, 2-way set associative  
2kB Data Cache, 2-way set associative  
Cache locking per line  
Programmable on a page basis to implement a write-through  
no write allocate, write-through write allocate, or write-back  
algorithms for cache management  
Compatible with a wide variety of operating systems  
SDRAM Controller (32-bit memory only)  
4 banks, non-interleaved  
Up to 256MB total SDRAM memory supported  
Implements full, direct control of discrete, SODIMM, or DIMM  
memories  
Supports 16Mb through 256Mb SDRAM device depths  
Automatic refresh generation  
Serial Peripheral Interface (SPI) master mode interface  
UART Interface  
16550 compatible UART  
Baud rate support up to 1.5M  
Memory & Peripheral Controller  
6 banks, up to 8MB per bank  
Local Bus Interface  
Supports 8-,16-, and 32-bit interfaces  
Supports Flash ROM, SRAM, dual-port memory, and  
peripheral devices  
Supports external wait-state generation  
8-bit boot PROM support  
Up to 66 MHz operation  
23-bit address bus  
32-bit data bus  
Direct control of local memory and peripherals  
Programmable system watch-dog timers  
Big or little endian support  
Flexible I/O timing protocols  
Interrupt Controller simplifies exception management  
Four general purpose 32-bit timer/counters  
Interrupt Contro  
32-bit Timers  
l
EJTAG  
In-Circuit Emulator Interface  
Programmable I/O  
SPI Control  
RISCore 32300  
Enhanced MIPS-II ISA Compatible  
Integer CPU  
RC5000  
CP0  
DMA Control  
UART  
Local  
Memory/IO  
Control  
32-page  
TLB  
IPBus  
Bridge  
SDRAM  
Control  
IDT  
Peripheral  
Bus  
8kB  
2-set  
2kB  
2-set, Lockable  
Lockable  
Instr. Cache  
Data Cache  
PCI Bridge  
Figure 1 RC32332 Block Diagram  
1 of 26  
March 13, 2001  
DSC 5914  
2001 Integrated Device Technology, Inc.  

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