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IDT79RC32V334-100BB8 PDF预览

IDT79RC32V334-100BB8

更新时间: 2024-11-21 20:10:31
品牌 Logo 应用领域
艾迪悌 - IDT 时钟微控制器外围集成电路
页数 文件大小 规格书
30页 486K
描述
RISC Microcontroller, 32-Bit, 100MHz, PBGA256, 17 X 17 MM, PLASTIC, BGA-256

IDT79RC32V334-100BB8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:17 X 17 MM, PLASTIC, BGA-256
针数:256Reach Compliance Code:not_compliant
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.49具有ADC:NO
地址总线宽度:32位大小:32
最大时钟频率:50 MHzDAC 通道:NO
DMA 通道:YES外部数据总线宽度:32
JESD-30 代码:S-PBGA-B256JESD-609代码:e0
长度:17 mm湿度敏感等级:3
I/O 线路数量:16端子数量:256
最高工作温度:85 °C最低工作温度:
PWM 通道:NO封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA256,16X16,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:3.5 mm
速度:100 MHz子类别:Microprocessors
最大压摆率:480 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:17 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

IDT79RC32V334-100BB8 数据手册

 浏览型号IDT79RC32V334-100BB8的Datasheet PDF文件第2页浏览型号IDT79RC32V334-100BB8的Datasheet PDF文件第3页浏览型号IDT79RC32V334-100BB8的Datasheet PDF文件第4页浏览型号IDT79RC32V334-100BB8的Datasheet PDF文件第5页浏览型号IDT79RC32V334-100BB8的Datasheet PDF文件第6页浏览型号IDT79RC32V334-100BB8的Datasheet PDF文件第7页 
RISCoreTM32300 Family  
Integrated Processor  
79RC32334  
Programmable I/O (PIO)  
Features  
Input/Output/Interrupt source  
RC32300 32-bit Microprocessor  
Individually programmable  
Up to 150 MHz operation  
SDRAM Controller (32-bit memory only)  
Enhanced MIPS-II Instruction Set Architecture (ISA)  
Cache prefetch instruction  
4 banks, non-interleaved  
Up to 256MB total SDRAM memory supported  
Implements full, direct control of discrete, SODIMM, or DIMM  
memories  
Conditional move instruction  
DSP instructions  
Supports big or little endian operation  
MMU with 32 page TLB  
Supports 16Mb through 256Mb SDRAM device depths  
Automatic refresh generation  
8kB Instruction Cache, 2-way set associative  
2kB Data Cache, 2-way set associative  
Cache locking per line  
Serial Peripheral Interface (SPI) master mode interface  
UART Interface  
Programmable on a page basis to implement a write-through  
no write allocate, write-through write allocate, or write-back  
algorithms for cache management  
Compatible with a wide variety of operating systems  
Two 16550 compatible UARTs  
Baud rate support up to 1.5M  
Modem control signals available on one channel  
Memory & Peripheral Controller  
Local Bus Interface  
6 banks, up to 64MB per bank  
Supports 8-,16-, and 32-bit interfaces  
Supports Flash ROM, SRAM, dual-port memory, and  
peripheral devices  
Up to 75 MHz operation  
26-bit address bus  
32-bit data bus  
Direct control of local memory and peripherals  
Programmable system watch-dog timers  
Big or little endian support  
Supports external wait-state generation  
8-bit boot PROM support  
Flexible I/O timing protocols  
Interrupt Controller simplifies exception management  
Four general purpose 32-bit timer/counters  
Block Diagram  
Interrupt Contro  
l
EJTAG  
Programmable I/O  
SPI Control  
In-Circuit Emulator Interface  
32-bit Timers  
RISCore32300  
RC5000  
Enhanced MIPS-II ISA Compatible  
Integer CPU  
CP0  
DMA Control  
Dual UART  
Local  
32-page  
TLB  
Memory/IO  
Control  
IPBus  
Bridge  
SDRAM  
Control  
IDT  
Peripheral  
Bus  
8kB  
2kB  
2-set, Lockable  
Data Cache  
2-set  
Lockable  
Instr. Cache  
PCI Bridge  
Figure 1 RC32334 Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 30  
May 2, 2002  
DSC 5701  
2001 Integrated Device Technology, Inc.  

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