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IDT79RC32T351-100DH PDF预览

IDT79RC32T351-100DH

更新时间： 2024-11-28 14:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 外围集成电路
页数 文件大小 规格书
42页 553K
描述
RISC Microprocessor, 32-Bit, 100MHz, PQFP208

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中文翻译

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IDT79RC32T351-100DH 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP针数：208
Reach Compliance Code：unknown风险等级：5.88
位大小：32JESD-30 代码：S-PQFP-G208
JESD-609代码：e0湿度敏感等级：3
端子数量：208最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP208,1.2SQ,20
封装形状：SQUARE封装形式：FLATPACK
电源：2.5,3.3 V认证状态：Not Qualified
速度：100 MHz子类别：Microprocessors
表面贴装：YES温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
uPs/uCs/外围集成电路类型：MICROPROCESSOR, RISCBase Number Matches：1

IDT79RC32T351-100DH 数据手册

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IDTTM InterpriseTM Integrated  
Communications Processor  
79RC32351  
◆
SDRAM Controller  
2 memory banks, non-interleaved, 512 MB total  
Features List  
–
–
–
–
–
–
◆
RC32300 32-bit Microprocessor  
32-bit wide data path  
Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips  
SODIMM support  
Stays on page between transfers  
Automatic refresh generation  
–
–
–
–
–
–
–
–
–
–
Enhanced MIPS-II ISA  
Enhanced MIPS-IV cache prefetch instruction  
DSP Instructions  
MMU with 16-entry TLB  
8kB Instruction cache, 2-way set associative  
2kB Data cache, 2-way set associative  
Per line cache locking  
Write-through and write-back cache management  
Debug interface through the EJTAG port  
Big or little endian support  
◆
Peripheral Device Controller  
–
26-bit address bus  
32-bit data bus with variable width support of 8-,16-, or 32-bits  
8-bit boot ROM support  
6 banks available, up to 64MB per bank  
Supports Flash ROM, PROM, SRAM, dual-port memory, and  
peripheral devices  
–
–
–
–
◆
◆
Interrupt Controller  
Allows status of each interrupt to be read and masked  
UARTs  
–
–
–
–
Supports external wait-state generation, Intel or Motorola style  
Write protect capability  
Direct control of optional external data transceivers  
–
–
Two 16550 Compatible UARTs  
Baud rate support up to 1.5 Mb/s  
◆
System Integrity  
◆
◆
Counter/Timers  
–
General Purpose I/O Pins (GPIOP)  
–
Programmable system watchdog timer resets system on time-  
out  
Three general purpose 32-bit counter/timers  
–
Programmable bus transaction times memory and peripheral  
transactions and generates a warm reset on time-out  
–
32 individually programmable pins:  
each pin programmable as input, output, or alternate function,  
input can be an interrupt or NMI source,  
input can also be active high or active low  
4 additional, auxiliary GPIO pins can be configured as input or  
output  
◆
DMA  
–
–
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14 DMA channels  
Services on-chip and external peripherals  
Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O  
transfers  
–
–
–
Supports flexible descriptor based operation and chaining via  
linked lists of records (scatter / gather capability)  
Supports unaligned transfers  
Block Diagram  
RC32300  
CPU Core  
Interrupt  
Controller  
:
:
10/100  
Ethernet  
Interface  
USB  
Interface  
ICE  
EJTAG  
MMU  
Watchdog  
Timer  
3 Counter  
Timers  
16 Channel  
DMA  
I. Cache  
D. Cache  
Controller  
Arbiter  
SDRAM &  
Device  
Controller  
GPIO  
Interface  
2 UARTS  
(16550)  
ATM  
Interface  
Ext. Bus  
Master  
Utopia 1 / 2  
GPIO Pins  
Memory &  
Peripheral Bus  
Ch. 2  
Ch. 1  
Serial Channels  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  
1 of 42  
May 25, 2004  
DSC 6053  
© 2002 Integrated Device Technology, Inc.  
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