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IDT79RC32T355-133DPI PDF预览

IDT79RC32T355-133DPI

更新时间: 2024-11-06 21:18:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟微控制器外围集成电路
页数 文件大小 规格书
46页 549K
描述
RISC Microcontroller, 32-Bit, 67MHz, PQFP208, 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, QFP-208

IDT79RC32T355-133DPI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, QFP-208针数:208
Reach Compliance Code:not_compliantECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.8
具有ADC:NO地址总线宽度:26
位大小:32最大时钟频率:67 MHz
DAC 通道:NODMA 通道:YES
外部数据总线宽度:32JESD-30 代码:S-PQFP-G208
JESD-609代码:e0长度:28 mm
湿度敏感等级:3I/O 线路数量:36
端子数量:208最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:NO
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:2.5,3.3 V认证状态:Not Qualified
座面最大高度:4.1 mm速度:67 MHz
子类别:Microprocessors最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:28 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

IDT79RC32T355-133DPI 数据手册

 浏览型号IDT79RC32T355-133DPI的Datasheet PDF文件第2页浏览型号IDT79RC32T355-133DPI的Datasheet PDF文件第3页浏览型号IDT79RC32T355-133DPI的Datasheet PDF文件第4页浏览型号IDT79RC32T355-133DPI的Datasheet PDF文件第5页浏览型号IDT79RC32T355-133DPI的Datasheet PDF文件第6页浏览型号IDT79RC32T355-133DPI的Datasheet PDF文件第7页 
79RC32355  
Preliminary Information*  
Integrated Communications  
Processor  
SDRAM Controller  
Features List  
2 memory banks, non-interleaved, 512 MB total  
RC32300 32-bit Microprocessor  
32-bit wide data path  
Enhanced MIPS-II ISA  
Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips  
SODIMM support  
Enhanced MIPS-IV cache prefetch instruction  
DSP Instructions  
Stays on page between transfers  
Automatic refresh generation  
MMU with 16-entry TLB  
8KB Instruction Cache, 2-way set associative  
2KB Data Cache, 2-way set associative  
Per line cache locking  
Peripheral Device Controller  
26-bit address bus  
32-bit data bus with variable width support of 8-,16-, or 32-bits  
8-bit boot ROM support  
Write-through and write-back cache management  
Debug interface through the EJTAG port  
Big or Little endian support  
6 banks available, up to 64MB per bank  
Supports Flash ROM, PROM, SRAM, dual-port memory, and  
peripheral devices  
Interrupt Controller  
Allows status of each interrupt to be read and masked  
Supports external wait-state generation, Intel or Motorola style  
Write protect capability  
I2C  
Flexible I2C standard serial interface to connect to a variety of  
peripherals  
Direct control of optional external data transceivers  
System Integrity  
Standard and fast mode timing support  
Configurable 7 or 10-bit addressable slave  
Programmable system watchdog timer resets system on time-  
out  
UARTs  
Programmable bus transaction times memory and peripheral  
transactions and generates a warm reset on time-out  
Two 16550 Compatible UARTs  
Baud rate support up to 115 Kbits  
DMA  
Counter/Timers  
16 DMA channels  
Three general purpose 32-bit counter/timers  
Services on-chip and external peripherals  
Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O  
transfers  
General Purpose I/O Pins (GPIOP)  
36 individually programmable pins  
Each pin programmable as input, output, or alternate function  
Input can be an interrupt or NMI source  
Supports flexible descriptor based operation and chaining via  
linked lists of records (scatter / gather capability)  
Supports unaligned transfers  
Input can also be active high, active low, or edge triggered  
Supports burst transfers  
Block Diagram  
Figure 1 RC32355 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 46  
March 29, 2001  
DSC 5900  
2001 Integrated Device Technology, Inc.  
*Notice: The information in this document is subject to change without notice  

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