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IDT79RC32T355-133DHII PDF预览

IDT79RC32T355-133DHII

更新时间： 2024-11-28 13:00:19
品牌 Logo 应用领域
艾迪悌 - IDT 微控制器和处理器外围集成电路通信时钟
页数 文件大小 规格书
47页 991K
描述
RISC Microprocessor, 32-Bit, 133MHz, PQFP208

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IDT79RC32T355-133DHII 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
位大小：32JESD-30 代码：S-PQFP-G208
JESD-609代码：e0湿度敏感等级：3
端子数量：208最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP208,1.2SQ,20
封装形状：SQUARE封装形式：FLATPACK
电源：2.5,3.3 V认证状态：Not Qualified
速度：133 MHz子类别：Microprocessors
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
uPs/uCs/外围集成电路类型：MICROPROCESSOR, RISCBase Number Matches：1

IDT79RC32T355-133DHII 数据手册

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IDTTM InterpriseTM Integrated  
Communications Processor  
79RC32355  
◆
SDRAM Controller  
2 memory banks, non-interleaved, 512 MB total  
Features List  
–
–
–
–
–
–
◆
RC32300 32-bit Microprocessor  
32-bit wide data path  
Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips  
SODIMM support  
Stays on page between transfers  
Automatic refresh generation  
–
–
–
–
–
–
–
–
–
–
Enhanced MIPS-II ISA  
Enhanced MIPS-IV cache prefetch instruction  
DSP Instructions  
MMU with 16-entry TLB  
8KB Instruction Cache, 2-way set associative  
2KB Data Cache, 2-way set associative  
Per line cache locking  
Write-through and write-back cache management  
Debug interface through the EJTAG port  
Big or Little endian support  
◆
Peripheral Device Controller  
–
26-bit address bus  
32-bit data bus with variable width support of 8-,16-, or 32-bits  
8-bit boot ROM support  
6 banks available, up to 64MB per bank  
Supports Flash ROM, PROM, SRAM, dual-port memory, and  
peripheral devices  
–
–
–
–
◆
◆
Interrupt Controller  
Allows status of each interrupt to be read and masked  
–
I C  
–
–
–
–
Supports external wait-state generation, Intel or Motorola style  
Write protect capability  
Direct control of optional external data transceivers  
2
2
Flexible I C standard serial interface to connect to a variety of  
peripherals  
◆
System Integrity  
–
–
Standard and fast mode timing support  
Configurable 7 or 10-bit addressable slave  
–
Programmable system watchdog timer resets system on time-  
out  
◆
UARTs  
–
Programmable bus transaction times memory and peripheral  
transactions and generates a warm reset on time-out  
–
–
Two 16550 Compatible UARTs  
Baud rate support up to 1.5 Mb/s  
◆
DMA  
◆
◆
Counter/Timers  
–
General Purpose I/O Pins (GPIOP)  
–
–
–
16 DMA channels  
Three general purpose 32-bit counter/timers  
Services on-chip and external peripherals  
Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O  
transfers  
–
36 individually programmable pins  
Each pin programmable as input, output, or alternate function  
Input can be an interrupt or NMI source  
–
–
–
–
Supports flexible descriptor based operation and chaining via  
linked lists of records (scatter / gather capability)  
Supports unaligned transfers  
Input can also be active high or active low  
–
–
Supports burst transfers  
Block Diagram  
RC32300  
CPU Core  
Interrupt  
Controller  
:
:
10/100  
USB  
Interface  
ICE  
EJTAG  
Ethernet  
Interface  
MMU  
Watchdog  
Timer  
3 Counter  
Timers  
16 Channel  
DMA  
I. Cache  
D. Cache  
Controller  
Arbiter  
SDRAM &  
Device  
Controller  
2
TDM  
Interface  
GPIO  
Interface  
ATM  
Interface  
2 UARTS  
(16550)  
I C  
Ext. Bus  
Master  
Controller  
Utopia 1 / 2  
2
TDM Bus  
GPIO Pins  
I C Bus  
Memory &  
Peripheral Bus  
Ch. 2  
Ch. 1  
Serial Channels  
Figure 1 RC32355 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 47  
May 25, 2004  
DSC 5900  
© 2004 Integrated Device Technology, Inc.  
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IDT79RC32T355-150DHGI IDT

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IDT79RC32T355-180DHI IDT

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 		RISCore32300TM Family System Controller Chip
IDT79RC32V134DSC IDT

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 		RISC Microcontroller, 32-Bit, 75MHz, PQFP208, 20 X 20 MM, 1.40 MM, PLASTIC, TQFP-208
IDT79RC32V134DSG IDT

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 		Multifunction Peripheral, PQFP208, PLASTIC, QFP-208
IDT79RC32V134DSGI IDT

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 		暂无描述

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