IDTTM InterpriseTM Integrated
Communications Processor
RC32336
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MMU
Device Overview
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16-entry TLB
The RC32336 device is a member of the IDT™ Interprise™ family of
integrated communications processors. It provides an effective solution
for small office/home office (SOHO) applications including gateways and
both single-band and dual-band wireless access points. Featuring a
MIPS compatible CPU core, the device also includes a memory
controller supporting SDRAM memory, a PCI interface featuring an on-
chip arbiter to support up to three external devices, a PCMCIA interface
that supports a single I/O device, and two integrated on-chip 10/100
Ethernet MACs to enable WAN and LAN connectivity.
Supports variable page sizes and enhanced write algo-
rithm
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Supports variable number of locked entries
8KB Instruction Cache
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2-way set associative
LRU replacement algorithm
4 word line size
Sub-block ordering
Word parity
Per line cache locking
The key features of the RC32336 enable SOHO applications at
unmatched price/performance points. The MIPS-compatible CPU core
has the required bandwidth to enable a WAP application with the latest
wireless security protocols, WPA and 802.11i, which include the enter-
prise-level user authentication schemes 802.1x and Extensible Authenti-
cation Protocol (EAP). The ability to connect and support the bandwidth
requirements of one or two WLAN modules is made possible by the high
bandwidth PCI and PCMCIA interfaces. Also, the device has been archi-
tected to provide high speed LAN to WAN routing bandwidth through the
Ethernet MACs while simultaneously driving data through the other on-
chip interfaces.
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2KB Data Cache
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2-way set associative
LRU replacement algorithm
4 word line size
Sub-block ordering
Byte parity
Per line cache locking
Can be programmed on a page basis to implement write-
through no write allocate, write-through write allocate, or
write-back algorithms
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Enhanced EJTAG and JTAG Interfaces
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Compatible with IEEE Std. 1149.1-1990
Features List
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RC32300 32-bit CPU core
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32-bit MIPS instruction set
Supports big or little endian operation
Block Diagram
MII
MII
SPI Bus
MIPS-32
CPU Core
Interrupt
Controller
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2 Ethernet
EJTAG
10/100
Interfaces
MMU
I. Cache
Bus/System
Integrity
Monitor
SPI
Controller
D. Cache
DMA
Controller
Arbiter
TM
IPBus
SDRAM &
PCI
Master/Target
Interface
Device
GPIO
Interface
UART
(16550)
Controllers
3 Counter
Timers
PCI Arbiter
(Host Mode)
PCI Bus
Memory &
Peripheral Bus
(including PCMCIA)
GPIO Pins
Serial Channel
Figure 1 RC32336 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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May 25, 2004
DSC 6405
© 2003 Integrated Device Technology, Inc.