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IDT79RC32K438-200BBI PDF预览

IDT79RC32K438-200BBI

更新时间： 2024-11-28 19:55:19
品牌 Logo 应用领域
艾迪悌 - IDT 外围集成电路
页数 文件大小 规格书
59页 622K
描述
RISC Microprocessor, 32-Bit, 200MHz, PBGA416

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中文翻译

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IDT79RC32K438-200BBI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA针数：416
Reach Compliance Code：unknown风险等级：5.92
位大小：32JESD-30 代码：S-PBGA-B416
JESD-609代码：e0端子数量：416
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA416,26X26,40封装形状：SQUARE
封装形式：GRID ARRAY电源：1.2,2.5,3.3 V
认证状态：Not Qualified速度：200 MHz
子类别：Microprocessors表面贴装：YES
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOMuPs/uCs/外围集成电路类型：MICROPROCESSOR, RISC
Base Number Matches：1

IDT79RC32K438-200BBI 数据手册

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IDTTM InterpriseTM Integrated  
Communications Processor  
79RC32438  
◆
Memory and Peripheral Device Controller  
Features  
–
Provides “glueless” interface to standard SRAM, Flash, ROM,  
dual-port memory, and peripheral devices  
◆
32-bit CPU Core  
–
–
MIPS32 instruction set  
–
Demultiplexed address and data buses: 16-bit data bus, 26-bit  
address bus, 6 chip selects, supports alternate bus masters,  
control for external data bus buffers  
Cache Sizes: 16KB instruction and data caches, 4-Way set  
associative, cache line locking, non-blocking prefetches  
16 dual-entry JTLB with variable page sizes  
3-entry instruction TLB  
–
–
–
–
–
–
–
–
–
–
–
Supports 8-bit and 16-bit width devices  
Automatic byte gathering and scattering  
3-entry data TLB  
Flexible protocol configuration parameters: programmable  
number of wait states (0 to 63), programmable postread/post-  
write delay (0 to 31), supports external wait state generation,  
supports Intel and Motorola style peripherals  
Write protect capability per chip select  
Programmable bus transaction timer generates warm reset  
when counter expires  
Max issue rate of one 32x16 multiply per clock  
Max issue rate of one 32x32 multiply every other clock  
CPU control with start, stop and single stepping  
Software breakpoints support  
Hardware breakpoints on virtual addresses  
Enhanced JTAG and ICE Interface that is compatible with v2.5  
of the EJTAG Specification  
–
–
–
Supports up to 64 MB of memory per chip select  
◆
DDR Memory Controller  
◆
◆
Counter/Timers  
–
Supports up to 2GB of DDR SDRAM  
2 chip selects (each chip select supports 4 internal DDR  
banks)  
Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit  
devices  
Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR  
SDRAM devices  
Data bus multiplexing support allows interfacing to standard  
DDR DIMMs and SODIMMs  
–
Three general purpose 32-bit counter timers  
–
–
–
–
–
PCI Interface  
–
–
32-bit PCI revision 2.2 compliant (3.3V only)  
Supports host or satellite operation in both master and target  
modes  
–
–
–
Support for synchronous and asynchronous operation  
PCI clock supports frequencies from 16 MHz to 66 MHz  
PCI arbiter in Host mode: supports 6 external masters, fixed  
priority or round robin arbitration  
Automatic refresh generation  
–
I O “like” PCI Messaging Unit  
2
Block Diagram  
MII  
MII  
MIPS-32  
CPU Core  
Interrupt  
Controller  
:
:
2 Ethernet  
EJTAG  
10/100  
Interfaces  
ICE  
MMU  
I. Cache  
On-Chip  
Memory  
D. Cache  
3 Counter  
Timers  
DMA  
Controller  
IPBusTM  
DDR &  
Arbiter  
Device  
DDR  
Controllers  
PCI  
Master/Target  
Interface  
I2C  
Controller  
SPI  
Controller  
GPIO  
Interface  
2 UARTS  
(16550)  
PCI Arbiter  
(Host Mode)  
I2C Bus  
PCI Bus  
SPI Bus  
GPIO Pins  
Memory &  
Peripheral Bus  
Ch. 2  
Ch. 1  
Serial Channels  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 59  
May 25, 2004  
DSC 6148  
© 2004 Integrated Device Technology, Inc.  
1234567...59

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