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IDT79RC32H435-350BCI PDF预览

IDT79RC32H435-350BCI

更新时间： 2024-11-29 14:42:47
品牌 Logo 应用领域
艾迪悌 - IDT 外围集成电路
页数 文件大小 规格书
53页 433K
描述
RISC Microprocessor, 32-Bit, 350MHz, PBGA256

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中文翻译

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IDT79RC32H435-350BCI 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：BGA针数：256
Reach Compliance Code：not_compliant风险等级：5.92
Is Samacsys：N位大小：32
JESD-30 代码：S-PBGA-B256JESD-609代码：e0
湿度敏感等级：3端子数量：256
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA256,16X16,40封装形状：SQUARE
封装形式：GRID ARRAY电源：1.2,2.5,3.3 V
认证状态：Not Qualified速度：350 MHz
子类别：Microprocessors表面贴装：YES
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOMuPs/uCs/外围集成电路类型：MICROPROCESSOR, RISC
Base Number Matches：1

IDT79RC32H435-350BCI 数据手册

 浏览型号IDT79RC32H435-350BCI的Datasheet PDF文件第2页浏览型号IDT79RC32H435-350BCI的Datasheet PDF文件第3页浏览型号IDT79RC32H435-350BCI的Datasheet PDF文件第4页浏览型号IDT79RC32H435-350BCI的Datasheet PDF文件第5页浏览型号IDT79RC32H435-350BCI的Datasheet PDF文件第6页浏览型号IDT79RC32H435-350BCI的Datasheet PDF文件第7页 
IDTTM InterpriseTM Integrated  
Communications Processor  
79RC32435  
◆
PCI Interface  
Device Overview  
–
–
32-bit PCI revision 2.2 compliant  
Supports host or satellite operation in both master and target  
modes  
Support for synchronous and asynchronous operation  
PCI clock supports frequencies from 16 MHz to 66 MHz  
PCI arbiter in Host mode: supports 6 external masters, fixed  
priority or round robin arbitration  
The 79RC32435 is a member of the IDT™ Interprise™ family of PCI  
integrated communications processors. It incorporates a high perfor-  
mance CPU core and a number of on-chip peripherals. The integrated  
processor is designed to transfer information from I/O modules to main  
memory with minimal CPU intervention, using a highly sophisticated  
direct memory access (DMA) engine. All data transfers through the  
RC32435 are achieved by writing data from an on-chip I/O peripheral to  
main memory and then out to another I/O module.  
–
–
–
–
◆
I2O “like” PCI Messaging Unit  
Ethernet Interface  
–
10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant  
Supports MII or RMII PHY interface  
Supports 64 entry hash table based multicast address filtering  
512 byte transmit and receive FIFOs  
Supports flow control functions outlined in IEEE Std. 802.3x-  
1997  
–
–
–
–
Features  
◆
32-bit CPU Core  
–
–
MIPS32 instruction set  
Cache Sizes: 8KB instruction and data caches, 4-Way set  
associative, cache line locking, non-blocking prefetches  
16 dual-entry JTLB with variable page sizes  
3-entry instruction TLB  
◆
DDR Memory Controller  
–
–
–
–
–
–
–
–
–
–
–
–
Supports up to 256MB of DDR SDRAM  
1 chip select supporting 4 internal DDR banks  
Supports a 16-bit wide data port using x8 or x16 bit wide DDR  
SDRAM devices  
3-entry data TLB  
Max issue rate of one 32x16 multiply per clock  
Max issue rate of one 32x32 multiply every other clock  
CPU control with start, stop, and single stepping  
Software breakpoints support  
Hardware breakpoints on virtual addresses  
ICE Interface that is compatible with v2.5 of the EJTAG Spec-  
ification  
–
–
–
Supports 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1Gb DDR  
SDRAM devices  
Data bus multiplexing support allows interfacing to standard  
DDR DIMMs and SODIMMs  
Automatic refresh generation  
Block Diagram  
MII/RMII  
2
I C Bus  
MIPS-32  
CPU Core  
Interrupt  
Controller  
:
:
2
I C  
Controller  
EJTAG  
ICE  
MMU  
I. Cache  
1 Ethernet  
10/100  
Interface  
D. Cache  
NVRAM  
Controller  
3 Counter  
Timers  
DMA  
Controller  
PMBus  
IPBusTM  
DDR  
Controllers  
DDR  
(16-bit)  
Arbiter  
PCI  
Master/Target  
Interface  
Memory & I/O  
Controller  
SPI  
Controller  
GPIO  
Interface  
1 UART  
(16550)  
Bus/System  
Integrity  
Monitor  
PCI Arbiter  
(Host Mode)  
PCI Bus  
SPI Bus  
Memory &  
Peripheral Bus (8-bit)  
GPIO Pins  
Serial Channel  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  
1 of 53  
January 19, 2006  
DSC 6214  
2005 Integrated Device Technology, Inc.  
1234567...53

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