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FQD13N06_09 PDF预览

FQD13N06_09

更新时间: 2024-11-20 12:23:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
9页 736K
描述
60V N-Channel MOSFET

FQD13N06_09 数据手册

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January 2009  
QFET®  
FQD13N06 / FQU13N06  
60V N-Channel MOSFET  
General Description  
Features  
These N-Channel enhancement mode power field effect  
transistors are produced using Fairchild’s proprietary,  
planar stripe, DMOS technology.  
This advanced technology has been especially tailored to  
minimize on-state resistance, provide superior switching  
performance, and withstand high energy pulse in the  
avalanche and commutation mode. These devices are well  
suited for low voltage applications such as DC/DC  
converters, high efficiency switching for power  
management in portable and battery operated products.  
10A, 60V, R  
= 0.14@V = 10 V  
DS(on) GS  
Low gate charge ( typical 5.8 nC)  
Low Crss ( typical 15 pF)  
Fast switching  
100% avalanche tested  
Improved dv/dt capability  
RoHS Compliant  
D
!
D
"
! "  
"
"
!
G
I-PAK  
FQU Series  
D-PAK  
FQD Series  
G
S
G
D
!
S
S
Absolute Maximum Ratings  
T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
FQD13N06 / FQU13N06  
Units  
V
V
I
Drain-Source Voltage  
60  
10  
DSS  
- Continuous (T = 25°C)  
Drain Current  
A
D
C
- Continuous (T = 100°C)  
6.3  
A
C
I
(Note 1)  
Drain Current  
- Pulsed  
40  
A
DM  
V
E
I
Gate-Source Voltage  
± 25  
85  
V
GSS  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
Single Pulsed Avalanche Energy  
Avalanche Current  
mJ  
A
AS  
10  
AR  
E
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
2.8  
mJ  
V/ns  
W
AR  
dv/dt  
7.0  
Power Dissipation (T = 25°C) *  
2.5  
P
A
D
Power Dissipation (T = 25°C)  
28  
W
C
- Derate above 25°C  
Operating and Storage Temperature Range  
0.22  
-55 to +150  
W/°C  
°C  
T , T  
J
STG  
Maximum lead temperature for soldering purposes,  
T
300  
°C  
L
1/8" from case for 5 seconds  
Thermal Characteristics  
Symbol  
Parameter  
Typ  
--  
Max  
4.5  
50  
Units  
°C/W  
°C/W  
°C/W  
R
R
R
Thermal Resistance, Junction-to-Case  
Thermal Resistance, Junction-to-Ambient *  
Thermal Resistance, Junction-to-Ambient  
θJC  
θJA  
θJA  
--  
--  
110  
* When mounted on the minimum pad size recommended (PCB Mount)  
©2009 Fairchild Semiconductor Corporation  
Rev. A2. January 2009  

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