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FDN338 PDF预览

FDN338

更新时间: 2024-09-26 22:31:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 晶体晶体管场效应晶体管
页数 文件大小 规格书
4页 88K
描述
P-Channel Logic Level Enhancement Mode Field Effect Transistor

FDN338 数据手册

 浏览型号FDN338的Datasheet PDF文件第2页浏览型号FDN338的Datasheet PDF文件第3页浏览型号FDN338的Datasheet PDF文件第4页 
March 1998  
FDN338P  
P-Channel Logic Level Enhancement Mode Field Effect Transistor  
General Description  
Features  
SuperSOTTM-3 P-Channel logic level enhancement mode  
power field effect transistors are produced using Fairchild's  
proprietary, high cell density, DMOS technology. This very  
high density process is especially tailored to minimize  
on-state resistance. These devices are particularly suited for  
low voltage applications in notebook computers, portable  
phones, PCMCIA cards, and other battery powered circuits  
where fast switching, and low in-line power loss are needed  
in a very small outline surface mount package.  
-1.6 A, -20 V, RDS(ON) = 0.13 W @ VGS = -4.5 V  
RDS(ON) = 0.18 W @ VGS = -2.5 V.  
Industry standard outline SOT-23 surface mount  
package using proprietary SuperSOTTM-3 design for  
superior thermal and electrical capabilities.  
High density cell design for extremely low RDS(ON)  
.
Exceptional on-resistance and maximum DC current  
capability.  
SuperSOTTM-3  
SuperSOTTM-8  
SuperSOTTM-6  
SOIC-16  
SO-8  
SOT-223  
D
D
S
S
G
SuperSOTTM-3  
G
Absolute Maximum Ratings TA = 25oC unless other wise noted  
Symbol Parameter  
FDN338P  
-20  
Units  
V
VDSS  
VGSS  
ID  
Drain-Source Voltage  
Gate-Source Voltage - Continuous  
±8  
V
Drain/Output Current - Continuous  
- Pulsed  
-1.6  
-5  
A
Maximum Power Dissipation  
(Note 1a)  
(Note 1b)  
0.5  
W
°C  
PD  
0.46  
TJ,TSTG  
Operating and Storage Temperature Range  
-55 to 150  
THERMAL CHARACTERISTICS  
Thermal Resistance, Junction-to-Ambient (Note 1a)  
Thermal Resistance, Junction-to-Case  
250  
75  
°C/W  
°C/W  
RqJA  
RqJC  
(Note 1)  
FDN338P Rev.D  
© 1998 Fairchild Semiconductor Corporation  

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