Datasheet > 存储 > DRAM> EDE5108GASA

EDE5108GASA

更新时间： 2024-11-08 06:55:55

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
45页	467K
描述
512M bits DDR-II SDRAM

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数据手册

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EDE5108GASA 数据手册

PRELIMINARY DATA SHEET

512M bits DDR-II SDRAM

EDE5104GASA (128M words × 4 bits)

EDE5108GASA (64M words × 8 bits)

Pin Configurations

Description

The EDE5104GA is a 512M bits DDR-II SDRAM

/xxx indicates active low signal.

60-ball FBGA

organized as 33,554,432 words × 4 bits × 4 banks.

The EDE5108GA is a 512M bits DDR-II SDRAM

organized as 16,777,216 words × 8 bits × 4 banks.

NU/ /RDQS

(NC)*

VDD

VSS

VSSQ /DQS VDDQ

It is packaged in 60-ball FBGA package.

DQ6

(NC)*

DQ7

DQS VSSQ

(NC)*

DM/RDQS

(DM)*

Features

VSSQ

• 1.8V power supply

VDDQ

DQ1 VDDQ

VSSQ DQ3

VREF VSS

CKE /WE

VDDQ DQ0 VDDQ

• Double-data-rate architecture: two data transfers per

clock cycle

DQ4

(NC)*

DQ5

DQ2 VSSQ

(NC)*

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

VDDL

VSSDL CK

VDD

/RAS

/CAS

/CK

/CS

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

BA0

A10

BA1

• Differential clock inputs (CK and /CK)

VDD

VSS

• DLL aligns DQ and DQS transitions with CK

transitions

VSS

VDD

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

A11

• Four internal banks for concurrent operation

• Data mask (DM) for write data

A12

• Burst lengths: 4 only

(Top view)

Note: ( )* marked pins are for EDE5104GA.

• /CAS Latency (CL): 3, 4

• Auto precharge operation for each burst access

• Auto refresh and self refresh modes

• 7.8µs maximum average periodic refresh interval

• 1.8V (SSTL_18 compatible) I/O

A0 to A12

BA0, BA1

DQ0 to DQ7

DQS, /DQS

RDQS, /RDQS

/CS

/RAS, /CAS, /WE

CKE

CK, /CK

VDD

VSS

VDDQ

VSSQ

VREF

VDDL

VSSDL

NC*¹

NU*²

Address input

Bank select address

Data-input/output

Differential data strobe

Differential data strobe for read

Chip select

Command input

Clock enable

Differential Clock input

Output mask

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

Reference supply voltage

Power for DLL circuit

Ground for DLL circuit

No connection

• Off-Chip-Driver Impedance Adjustment for better

signal quality.

• Programmable RDQS, /RDQS output for the

compatibility to × 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation.

• FBGA package is lead free solder (Sn-Ag-Cu)

Not usable

Notes: 1. Not internally connected with die.

2. Don't connect. Internally connected with die.

Document No. E0203E41 (Ver. 4.1)

Date Published February 2006 (K) Japan

URL: http://www.elpida.com

This product became EOL in March, 2004.

Elpida Memory, Inc. 2001-2006

12 3 4 5 6 7...45

中文翻译

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与EDE5108GASA相关器件

型号	品牌	获取价格	描述	数据表
EDE5108GASA-4A-E	ELPIDA	获取价格	512M bits DDR-II SDRAM
EDE5108GASA-5A-E	ELPIDA	获取价格	512M bits DDR-II SDRAM
EDE5108GBSA	ELPIDA	获取价格	512M bits DDR-II SDRAM
EDE5108GBSA-4A-E	ELPIDA	获取价格	512M bits DDR-II SDRAM
EDE5108GBSA-5A-E	ELPIDA	获取价格	512M bits DDR-II SDRAM
EDE5116ABSA-5A-E	ELPIDA	获取价格	DDR DRAM, 32MX16, 0.5ns, CMOS, PBGA84, MICRO, FBGA-84
EDE5116ABSE	ELPIDA	获取价格	512M bits DDR2 SDRAM
EDE5116ABSE-4A-E	ELPIDA	获取价格	512M bits DDR2 SDRAM
EDE5116ABSE-4C-E	ELPIDA	获取价格	DDR DRAM, 32MX16, 0.6ns, CMOS, PBGA84, FBGA-84
EDE5116ABSE-5A-E	ELPIDA	获取价格	暂无描述

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